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International Conference on High Performance Computing & Simulation (HPCS)

作者： Ping Yao Hong An Mu Xu Gu Liu Xiaoqiang Li Yaobin Wang Wenting Han School of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

GPUs have recently been used to accelerate data-parallel applications for they provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power. Most of those applications use CPU as a controller who decides when GPUs run the computing-intensive tasks. This CPU-control-GPU-compute pattern wastes much of CPU's computational power. In this paper, we present a new CPU-GPU cooperative pattern for bioinformatics applications which can use both of CPU and GPU to compute. This pattern includes two parts: 1) the load-balanced data structure which manages data to keep the computational efficiency of GPU high enough when the length distribution of sequences in a sequence database is very uneven; 2) multi-threaded code partition which schedules computing on CPU and GPU in a cooperative way. Using this pattern, we develop CuHMMer based on HMMER which is one of the most important algorithms in bioinformatics. The experimental result demonstrates that CuHMMer get 13x to 45x speed up over available CPU implementations and could also outperform the traditional CUDA implementations which use CPU-control-GPU-compute pattern.

关键词： Hidden Markov models Graphics processing unit Databases Kernel computer architecture

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A scheduling algorithm for private clouds

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Journal of Convergence Information Technology 2011年第7期6卷 1-9页

作者： Li, Jiandun Peng, Junjie Zhang, Wu School of Computer Engineering and Science Shanghai University Shanghai 200072 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing 100190 China

In contrast with public clouds, private clouds have some unique features, especially when related to workflow scheduling. Of course, the tradeoff problem between power and performance remains to be one of the key concerns. Based on our previous research, in this paper, we propose a hybrid energy-efficient scheduling algorithm using dynamic migration. The experiments show that it can not only reduce the response time, conserve more energy, but also achieve higher level of load balancing.

关键词： Scheduling algorithms

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The Mapping Framework and Optimizing Strategy for Block Cryptography Algorithms on Cell Broadband Engine

The Mapping Framework and Optimizing Strategy for Block Cryp...

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Mu Xu Hong An Gu Liu Yaobin Wang Guang Xu Ping Yao Xiurui Hao Wenting Han School of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

The Cell Broadband Engine is a typical heterogeneous chip multiprocessor which provides potential high performance for computing-intensive applications. Our researches focus on how to use Cell to speed up block cryptography applications. In this paper, we propose a mapping framework for block cryptography working in ECB mode and corresponding optimizing strategy. We take four algorithms(RC5, 3DES, AES, and Twofish) as benchmark and implement these four algorithms using Cell programming language. In order to enhance the performance, we present an optimizing strategy and evaluate the effects of the optimizing methods including compiler optimization, dual buffering, vectorization, and loop unrolling. The experiments indicate that all these four algorithms can obtain 5-20 times speedup compared with traditional processors, which shows that our mapping framework and optimizing strategy are effective for the block cryptography algorithms.

关键词： Engines Elliptic curve cryptography computer architecture Optimizing compilers Optimization methods Distributed computing Application software High performance computing computer applications Clocks

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Characterizing Betweenness Centrality Algorithm on Multi-core architectures

Characterizing Betweenness Centrality Algorithm on Multi-cor...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Dengbiao Tu Guangming Tan Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

This paper presents an in-depth analysis of characterization for an irregular application - computing betweenness centrality (BC) - on multicore architectures. BC algorithm is widely used in large scale graph analysis applications, which play an increasingly important role in high performance computing community. Through a joint study of architecture and application, we find that dynamically non-contiguous memory access, unstructured parallelism and low arithmetic intensity in BC program pose an obstacle to an efficient execution on parallel architectures. The experimental results report a comparison between Intel Clovertown and Sun Niagara1 for running such irregular program. Finally, several implications on multicore architecture and programming are proposed.

关键词： computer architecture Multicore processing computer applications Large-scale systems Performance analysis Algorithm design and analysis High performance computing Parallel processing Arithmetic Parallel architectures

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NICFlex: A Functional Verification Accelerator for An RTL NIC Design

NICFlex: A Functional Verification Accelerator for An RTL NI...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Xianyang Jiang Xiaomin Li Yue Tian Kai Wang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Chinese Academy of Sciences China

A short time-to-market is very important for a chip, and verification takes the most (about 70%) of its design time. Network interface controller (NIC) is a key component for a supercomputer and other computing systems. To reduce verification time for such a market-demanding product plays a great role in relevant system design. In this paper, a functional verification accelerator NICFlex is presented for a register transfer level (RTL) NIC design. NICFlex accelerates verification process by both a software part and a hardware part. The software part runs as a simulation thread, and the hardware part is mapped into field programmable gate array (FPGA) logic together with a NIC wrapper. Compared to a conventional simulation verification method using ModelSim, NICFlex can accelerate the functional verification of an RTL NIC design for hundreds of times or more. With extension, NICFlex is promising for any functional verification acceleration of a generic RTL design.

关键词： Acceleration Hardware Field programmable gate arrays Programmable logic arrays Time to market Network interfaces Control systems Supercomputers computer interfaces computer networks

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Reliability Optimization of Reconfigurable FPGA Based on Second-Order Approximation Domain-Partition

Reliability Optimization of Reconfigurable FPGA Based on Sec...

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International Conference on Embedded Software and systems

作者： Mi Zhou Lihong Shang Yu Hu School of Computer Science and Engineering Beihang University Beijing China Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424443598

The problem of planning the overlaps of multiple alternative configurations is critical to maximize the reliability of a reconfigurable fault-tolerant system based on field programmable gate arrays. To address the problem, an unnecessary assumption made in previous work is removed and a second-order approximation domain-partition method is proposed. Experimental results on ITC99 benchmark circuits demonstrate the proposed technique outperforms previous work in failure rate with less memory cost to store configurations.

关键词： Field programmable gate arrays Circuit faults Fault tolerant systems Redundancy Tiles Embedded software computer science Reliability engineering Costs computer architecture

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Localizing Loads Execution in a Data Cache Distributed Processor architecture

Localizing Loads Execution in a Data Cache Distributed Proce...

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International Association of computer Science and Information Technology - Spring Conference, IACSITSC

作者： Ruiling Dou Hong An Rui Guo Wenting Han Ming Cong Yongqing Ren Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

To scale with the on-chip wire delay, the inside of a processor will further be partitioned into more small banks. As the amount of data cache bank scales, the load routing latency will contribute a considerable portion to program executing time. In a tiled processor like T-Flex, we observed that the average load routing latency (hit in data cache) can be largely reduced (by 72.1%) when data is perfectly placed in where the load issues. To reduce the long routing latency of critical loads, we give out a solution for localizing load execution at issuing side in this paper. However, this method will induce overhead of data copies and extra communications to maintain coherence and memory order. We explore the design space for localizing data access, with special respect to maximizing benefits at expense of relatively small overhead. We observed the access frequency and load store behaviors for different copies vary largely, with large amount of successive load accesses concentrating on small amount of data blocks. Our experiments show that with special replication and data copy invalidation strategies, copying overhead will be controlled while maintaining considerable performance profits.

关键词： Delay Tiles computer architecture Routing Processor scheduling computer science Springs Wire Space exploration Art

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A Program Behavior Study of Block Cryptography Algorithms on GPGPU

A Program Behavior Study of Block Cryptography Algorithms on...

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Japan-China Joint Workshop on Frontier of computer Science and Technology (FCST)

作者： Gu Liu Hong An Wenting Han Guang Xu Ping Yao Mu Xu Xiurui Hao Yaobin Wang Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Recently many studies have been made to map cryptography algorithms onto graphics processors (GPU), and gained great performances. This paper does not focus on the performance of a specific program exploited by using all kinds of optimization methods algorithmically, but the intrinsic reason which lies in GPU architectural features for this performance improvement. Thus we present a study of several block encryption algorithms(AES, TRI-DES, RC5, TWOFISH and the chained block cipher formed by their combinations) processing on GPU using CUDA. We introduce our CUDA implementations, and investigate the program behavioral characteristics and their impacts on the performance in four aspects. We find that the number of threads used by a CUDA program can affect the overall performance fundamentally. Many block encryption algorithms can benefit from the shared memory if the capacity is large enough to hold the lookup tables. The data stored in device memory should be organized purposely to avoid performance degradation. Besides, the communication between host and device may turn out to be the bottleneck of a program. Through these analyses we hope to find out an effective way to optimize a CUDA program, as well as to reveal some desirable architectural features to support block encryption applications better.

关键词： Cryptography computer architecture Acceleration Runtime computer science Parallel processing Hardware Laboratories computer graphics Optimization methods

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Outlier Detection for Learning-Based Optimizing Compiler

Outlier Detection for Learning-Based Optimizing Compiler

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Japan-China Joint Workshop on Frontier of computer Science and Technology (FCST)

作者： Shun Long Weiheng Zhu Department of Computer Science Jinan University Guangzhou China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

Modern compilers use machine learning to find from their prior experience useful heuristics for new programs encountered in order to accelerate the optimization process. However, prior experience might not be applicable for outlier programs with unfamiliar code features. This paper presents a Reverse K-nearest neighbor (RKNN) algorithm based approach for outlier detection. The compiler can therefore launch a search within an optimization space when outlier programs are encountered, or directly apply its experience to non-outliers. Preliminary experimental results demonstrate the effectiveness of the approach.

关键词： Optimization Program processors Training Kernel Benchmark testing Arrays Nearest neighbor searches

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Luminance and Chrominance Parallelization of H.264/AVC Decoding on a Multi-core Processor

Luminance and Chrominance Parallelization of H.264/AVC Decod...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaofu Meng Xiang Gao Qian Yu Shuangshuang Zhang Xiaochun Zhang Jing Huang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Loongson Technology Corporation Limited Beijing China

This paper proposes a novel method to optimizing H.264 decoding on multi-core processors by exploiting color component level parallelism. Compared with sequential decoding and macro-block level parallelism, the proposed method achieves optimal balance between performance and scalability. The optimization scheme is mapped on a 64-bit MIPS multi-core processor, and is evaluated with standard test streams. Experimental results show that the method improves video decoding performance by 2 times on average without increasing memory consumption, and could be easily applied on other multi-core processors.

关键词： Decoding Streaming media Multicore processing Pipelines Video coding Parallel processing Standards

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