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On-Chip Generating FPGA Configuration Bitstreams to Reduce Applycation-Independent Test Time

On-Chip Generating FPGA Configuration Bitstreams to Reduce A...

The 4th International Workshop on Advanced Technologies in Programmable system on Chip(第四届片上可编程系统前沿技术研讨会)

作者： Da Wang Fei Wang Paolo Ienne Yu Hu Dongrui Fan Haigang Yang Key Laboratory of Computer System and Architecture Institute of Computing TechnologyCASBeijing100190China System on Programmable Chip Research DepartmentInstitute of ElectronicsCASBeijing100190China Processor Architecture LaboratoryEPFLLausanneSwitzerland

FPGA application independent test is very time-consuming due to repetitively loading of test configuration bitstreams into the FPGA and applying test *** shows that over 95%of FPGA application independent test time is spent on loading the test configuration ***,reducing the number of loading times could significantly reduce the FPGA test *** this paper,a new approach which can significantly reduce the FPGA test time will be *** this new approach,a configuration SRAM routing strategy is used first to enhance the correlation of the test bitstream configurations,then,on-chip test configuration generation structures are designed to transform a test bitstream configuration into other ones within limited *** results show that the proposed technique can at least reduce the configuration loading time by 81%,while getting 100%test *** hardware overhead is less than 1.2%upon the whole chip without any performance penalty.

关键词： FPGA test test configuration generation design-for-testability

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PartitionSim: A parallel simulator for many-cores

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Jisuanji Xuebao/Chinese Journal of computers 2011年第11期34卷 2084-2092页

作者： Jiao, Shuai Xu, Wei-Zhi Tang, Shi-Bin Fan, Dong-Rui Sun, Ning-Hui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acad. of Sci. Beijing 100190 China Graduate University of Chinese Acad. of Sci. Beijing 100049 China

This paper introduces PartitionSim, a parallel simulator for future thousand-core processors with software-managed cache coherence. The purpose of PartitionSim is to improve the simulation performance of many-core architectures at the expense of little accuracy sacrifice. To achieve this goal, we propose a novel technique: timing partition. Timing partition is based on such an observation: in a target system, interacting components communicate with each other and impose simulation synchronization while non-interacting components don't communicate with each other and allow asynchronous simulation. It divides the target timing models into two groups: non-interacting group and interacting group. Non-interacting timing models are simulated by host threads that synchronize little with each other to improve speed and hurt little accuracy, while interacting timing models are simulated by host threads that synchronize strictly with each other to preserve accuracy. Using PartitionSim, We have simulated a target composed of thousands of cores on a 16-core SMP machine. The evaluation results show that PartitionSim scales well with near linear speedup and has considerable performance (up to 25MIPS) at the expense of little accuracy sacrifice (average 0.92%).

关键词： Timing circuits

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On synchronization and evaluation method of chipped many-core processor

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Jisuanji Xuebao/Chinese Journal of computers 2010年第10期33卷 1777-1787页

作者： Xu, Wei-Zhi Song, Feng-Long Liu, Zhi-Yong Fan, Dong-Rui Yu, Lei Zhang, Shuai Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acad. of Sci. Beijing 100190 China Graduate University of Chinese Acad. of Sci. Beijing 100039 China

Synchronization schemes are critical for on-chip multi-core and many-core processor to execute correctly and communicate cooperatively. The efficiency of the synchronization is very important for the processor. In this paper, for on-chip many-core architecture, three types of synchronization schemes are proposed. That is, two types of coarse-grain synchronization schemes based on dedicated hardware support and atomic operation, and a fine-grain synchronization scheme based on Full/Empty bit. Then, the evaluation criterions and methods are proposed, in which quantitative evaluation micro-benchmarks are designed for coarse-grain synchronization schemes. Finally, the coarse-grain synchronization schemes are evaluated via a many-core architecture simulator, i.e., Godson-T, and AMD Opteron commercial on-chip multi-processor using pThread multi-thread program model. The results show that hardware support improves the performance of the synchronization obviously for on-chip many-core processor, and the performance loss of the traditional synchronization scheme based on atomic instructions is caused by the waiting cost of load imbalance and serialization on synchronization point mostly.

关键词： Synchronization

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CHMasters: A Scalable and Speed-Efficient Metadata Service in Distributed File system

CHMasters: A Scalable and Speed-Efficient Metadata Service i...

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Min Xu Junrui Zhou Wei Zhou Hong An Department of Computer Science and Technology University of Science and Technology of China Hefei China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China

Distributed file system (DFS) is playing important roles of supporting large distributed data-intensive applications to meet storage needs. Typically, the design of DFS, such as GFS in Google, DMS in Cisco and TFS in Alibaba, is driven by observations of specific application workloads, internal demands and technological environment. In such systems, the metadata service is a critical factor that can affect the file system performance and availability to a great degree. Five requirements have been summarized for the metadata service: location transparent file service, smart director, efficient speed, strong scalability and friendly collaborator. In this paper, we present metadata service module called CH Masters in our DFS. Consistent hashing protocol is used to relieve potential hot spots on name servers. Files' metadata and master nodes are mapped into the same hash space by consistent hash function. And then files' metadata are scattered to master nodes by clockwise "closest" principle. Chunk server acts as a client when report its chunks info. Only a small proportion of files' metadata will be rehashed when master nodes state change. A new scalable file mapping strategy is also proposed to map file sizes from few MB to several GB efficiently. After intensive experiments, it shows CH Masters is satisfying the above five requirements.

关键词： Protocols File systems Google Servers computer architecture Clocks Testing

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A SAT-Based Pattern Generation Method for Diagnosis Multiple Scan Chain Faults

A SAT-Based Pattern Generation Method for Diagnosis Multiple...

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2011 2nd International Conference on Advanced Measurement and Test (AMT 2011)

作者： Fei Wang Da Wang Haigang Yang System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Scan chain design is a widely used design-for-testability(DFT) technique to improve test and diagnosis qualityHowever, failures on scan chain itself account for up to 30% of chip failuresTo diagnose root causes of scan chain failures in a short period is vital to failure analysis process and yield improvementsAs the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysisIn this paper, a SAT-based technique is proposed to generate patterns to diagnose scan chain faultsThe proposed work can efficiently generate high quality diagnostic patterns to achieve high diagnosis resolutionMoreover, the computation overhead of proving equivalent faults is reducedExperimental results on ISCAS'89 benchmark circuits show that the proposed method can reduce the number of diagnostic patterns while achieving high diagnosis resolution.

关键词： scan chain,testing,diagnosis,boolean satisfiability(SAT),very large scale integration

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Small Delay Fault Simulation for Sequential Circuits

Small Delay Fault Simulation for Sequential Circuits

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Pacific Rim International Symposium on Dependable Computing

作者： Li Liu Jishun Kuang Huawei Li School of Computer and Communication Hunan University Changsha China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is presented. The sizes of the faults are less than one system clock cycle. For our method, the delay distribution in the CUT is considered, and the fault size is quantized as times of the propagation delay in an inverter. By a waveform simulation based on Boolean process, the simulator is able to show the time interval that the fault affects and determine whether the propagation delay exceeds the system clock cycle. It might give ATPG a little of useful information.

关键词： Circuit faults Circuit simulation Sequential circuits Electrical fault detection Fault detection Propagation delay Clocks Circuit testing Inverters Automatic test pattern generation

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A Low Overhead On-Chip Path Delay Measurement Circuit

A Low Overhead On-Chip Path Delay Measurement Circuit

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Asian Test Symposium (ATS)

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy.

关键词： Integrated circuit measurements Delay effects Area measurement Time measurement Delay lines Electrical fault detection Fault detection Debugging Circuit faults Added delay

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Test and repair flow for shared BISR in asynchronous multi-processors

Test and repair flow for shared BISR in asynchronous multi-p...

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20th IEEE International Symposium on Asynchronous Circuits and systems, ASYNC 2014

作者： Wang, Gang Wang, Xu Chen, Xinke Xue, Shuangbai Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China Shandong Eway Information and Technology Co. Ltd China

ISBN: (纸本)9781479937899

We present a hierarchical test and repair flow for shared BISR (Built-In Self-Repair) in asynchronous multi-processors. The flow partitions the memories local to a processor in groups and treats the groups as a whole when doing the repair. The flow runs automatically with few interventions except at the beginning stage. It can be used effectively for practical industrial test and repair. Its test time is as good as equivalent to that of parallel BISR, while its test power is substantially lower, about 40% that of parallel repair. It also has a superior repair rate, about 11-12% better compared to sequential and parallel BISR. © 2014 IEEE.

关键词： Repair

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Test and Repair Flow for Shared BISR in Asynchronous Multi-processors

Test and Repair Flow for Shared BISR in Asynchronous Multi-p...

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International Symposium on Advanced Research in Asynchronous Circuits and systems

作者： Gang Wang Xu Wang Xinke Chen Shuangbai Xue Key Laboratory of Computer System and Architecture Loongson Technology Corporation Limited Beijing Shandong Eway Information & Technology CO. Ltd

关键词： Maintenance engineering Program processors Synchronization Built-in self-test computers system-on-chip

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High efficient memory race recording scheme for parallel program deterministic replay under multi-core architecture

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2012年第1期49卷 64-75页

作者： Liu, Lei Huang, He Tang, Zhimin Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100049 China MIPS Technologies Shanghai 210021 China

Current shared memory multi-core and multiprocessor systems are nondeterministic. When these systems execute a multithreaded application, even if supplied with the same input, they could produce a different output each time. It frustrates debugging and limits the ability to properly test multithreaded code, and is becoming a major stumbling block to the much-needed widespread adoption of parallel programming. The support for deterministic replay of multithreaded execution is greatly helpful in finding concurrency bugs. A memory race recording scheme, named Rainbow, is proposed. Its core idea is to make inter-thread communications fully deterministic. The unique feature of Rainbow is that it precisely sets up happens-before relationships between conflicting memory operations among different threads. By using effective, bloom-filter based, coherence history queue, Rainbow removes redundant happens-before relations implied in the already generated log and enables a compact log. Rainbow adds the modest hardware to the base multi-core processors, and the coherence protocol is unmodified. The analysis results show that Rainbow reduces the log size by 17% of a state-of-the-art scheme, and the records execution speed is similar to that of release consistency (RC) execution and replays at about 93% of its speed. The determinism can be provided with little performance cost using our architecture proposals on the state-of-the-art hardware, and the software-only approaches can be utilized on existing systems without problem.

关键词： Parallel programming

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