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第十二届全国容错计算学术会议

作者： WANG Fei HU Yu LI Xiaowei Graduate School of Chinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.

关键词： test diagnosis scan chain diagnosis design for diagnosis (DFD)

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Dynamically tolerating and detecting asymmetric races

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2014年第8期51卷 1748-1763页

作者： Wang, Wenwen Wu, Chenggang Ratanaworabhan, Paruj Yuan, Xiang Wang, Zhenjiang Li, Jianjun Feng, Xiaobing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China University of Chinese Academy of Sciences Beijing100049 China Faculty of Engineering Kasetsart University Bangkok10900 Thailand

Asymmetric races are a common type of data races. They are triggered when a thread accesses a shared variable in a critical section, and another thread accesses the same shared variable not in any critical section, or in a critical section guarded by a different lock. Asymmetric races in multi-threaded programs are usually harmful. To solve the problem introduced by asymmetric races, ARace is proposed. ARace utilizes shared variable protecting and write buffer to dynamically tolerate and detect asymmetric races. Shared variable protecting is used to protect shared variables that are read-only and read-before-write in critical sections, and these shared variables should not be modified out of critical sections;write buffer is used to buffer the writing operations to shared variables in critical sections. ARace can not only tolerate asymmetric races triggered by shared variable accesses in and out of critical sections, but also detect asymmetric races triggered by shared variable accesses in concurrent critical sections. ARace can be directly applied to binary code and requires neither additional compiler support nor hardware support. In addition, an implementation based on dynamic binary instrumentation is also proposed. The experimental results demonstrate that ARace guarantees the tolerance and detection of asymmetric races while incurring acceptable performance and memory overhead.

关键词：非对称数据竞争容忍和检测写缓冲区页保护动态二进制插桩

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Scaling the Performance of Tiled Processor architectures with On-Chip-Network Topology

Scaling the Performance of Tiled Processor Architectures wit...

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The Second International Joint Conference on Computational Science and Optimization(CSO 2009)(2009 国际计算科学与优化会议)

作者： Yongqing Ren Hong An Ming Cong Guang Xu Li Wang Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

The trend in wire delays due to resistance is becoming a significant problem for microprocessor designers, forcing radically new tiled microprocessor architecture designs. This type of architecture will necessarily incorporate on-chip networks topology. This paper examines a few of the possible on-chip network topology in the context of tiled processor architectures. Firstly, by investigating some proposed tiled processor architecture, we observe that the on-chip network interconnecting is the critical design point in the architectures. After that, we discuss the candidate topologies of on-chip network topology that satisfy these properties. Finally, a detailed experimental evaluation of these networks topology is presented to highlight the scalability and performance of these tiled processor architectures. Results show that we can achieve performance improvement by modifying basic mesh appropriately according to the granularity of the tile within technology restrictions.

关键词： Tiles Network topology Wire Network-on-a-chip Microprocessors Delay Switches computer architecture Process design Registers

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Shape Analysis of Volume Models by Euclidean Distance Transform and Moment Invariants

Shape Analysis of Volume Models by Euclidean Distance Transf...

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10th IEEE International Conference on computer Aided Design and computer Graphics(第十届CAO/Graphics国际会议)

作者： Dong Xu Hua Li Key Laboratory of Intelligent Information Processing Key Laboratory of Computer System and Architecture National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese

In this paper,volume models are obtained from closed surface models by an accurate voxelization method which can handle the hidden cavities. This kind of 3D binary images is then converted to gray-level images by a fast Euclidean distance transform (EDT).Moment invariants (MIs) which are invariant shape descriptors under similarity transformations,are then computed based on the gray images. Applications in shape analysis area such as principal axis determination,skeleton and medial axis extraction,and shape retrieval can be carried out base on EDT and MIs.

关键词： Shape Euclidean distance Skeleton Principal component analysis Laboratories Image converters Data mining Computed tomography Clouds Iterative closest point algorithm

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MemoryIO: An Extended I/O Technology in Embedded systems

MemoryIO: An Extended I/O Technology in Embedded Systems

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International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaojun Yang Tao Liu Fei Chen Hailiang Cheng National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Graduate University of Advanced Studies (SOKENDAI) Beijing China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyNational Research Center for Intelligent Computing Systems Chinese Academy and Sciences China

MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory system is absolutely necessary in any embedded system, and not all embedded systems integrate HyperTransport (HT), PCI Express or RapidIO interface, the MemoryIO based interconnect in embedded systems has more universalities compared with that based on HT, PCI Express or RapidIO. MemoryIO can not only thoroughly compensates for the lack of high performance data transfer channel, but also efficiently utilizes the memory bus bandwidth and the direct memory access (DMA) engine to reduce the latency for data transfer in embedded systems. This paper discusses some key technologies of MemoryIO, and presents its application in DCNet and the implementation of MemoryIO IP core. The MemoryIO technology can be used in various systems, but not limited to embedded systems.

关键词： Embedded system Payloads Switches Clocks Storage area networks Physical layer Protocols

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Dynamic Resource Allocation Based on User experience in Virtualized Servers

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Procedia Engineering 2011年 15卷 3780-3784页

作者： Wei Zhang Jiajun Liu Ying Song Mingfa Zhu Limin Xiao Yuzhong Sun Li Ruan State Key Laboratory of Software Development Environment Beijing 100191 China School of Computer Science and Engineering Beihang University Beijing 100191 China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing Institute of Computing Technology Chinese Academy of Sciences Beijing China

Web workloads are known to vary dynamically with time which poses a challenge to resource allocation among the applications. In this paper, we argue that the existing dynamic resource allocation based on resource utilization has some drawbacks in virtualized servers. Dynamic resource allocation directly based on real-time user experience is more reasonable and also has practical significance. To address the problem, we propose a system architecture that combines real time measurements and analysis of user experience for resource allocation. We evaluate our proposal using Webbench. The experiment results show that these techniques can judiciously allocate system resources.

关键词： resource allocation virtualized servers user experience

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Study on Fine-Grained Synchronization in Many-Core architecture

Study on Fine-Grained Synchronization in Many-Core Architect...

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ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD)

作者： Lei Yu Zhiyong Liu Dongrui Fan Fenglong Song Junchao Zhang Nan Yuan Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The synchronization between threads has serious impact on the performance of many-core architecture. When communication is frequent, coarse-grained synchronization brings significant overhead. Thus, coarse-grained synchronization is not suitable for this situation. However, the overhead of fine-grained synchronization is still small when the communication is frequent. For the many-core architecture which supports fine-grained synchronization with on-chip storage, we propose fine-grained synchronization algorithms for scientific computation application 2-D wavefront and LU decomposition. At first, according to the memory access mode, an efficient method of data allocation is proposed. Then, way of thread partition and synchronization are discussed. Finally, we estimate the two algorithms based on Godson-T many-core architecture. The results of experiments show that the relative speedup is almost linear and the execution time is only 53.2 % of the coarse-grained synchronization. After the global barriers are eliminated, LU decomposition achieved 13.1% performance improvement. Moreover, the experiments prove that the fine-grained mechanism is able to improve the performance of processor and it has a good scalability.

关键词： Frequency synchronization computer architecture Yarn Parallel processing Distributed computing Concurrent computing Delay Programming profession Partitioning algorithms Wire

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Cross-layer optimized placement and routing for FPGA soft error mitigation

Cross-layer optimized placement and routing for FPGA soft er...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Keheng Huang Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. Our analysis shows that the statistical variation of the application level factor is significant. Hence in this work, we first propose a cube-based analysis to efficiently and accurately evaluate the application level factor. And then we propose a cross-layer optimized placement and routing algorithm to reduce the SER by incorporating the application level and the physical level factor together. Experimental results show that, the average difference of the application level factor between our cube-based method and Monte Carlo golden simulation is less than 0.01. Moreover, compared with the baseline VPR placement and routing technique, the cross-layer optimized placement and routing algorithm can reduce the SER by 14% with no area and performance overhead.

关键词： Routing Wires Circuit faults Field programmable gate arrays Monte Carlo methods Algorithm design and analysis Accuracy

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Empirical design bugs prediction for verification

Empirical design bugs prediction for verification

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Design, Automation and Test in Europe Conference and Exhibition

作者： Qi Guo Tianshi Chen Haihua Shen Yunji Chen Yue Wu Weiwu Hu Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is to expose as many bugs as possible. In this paper, we propose a novel verification methodology that leverages the early bug prediction of a DUV to guide and assess related verification process. To be specific, this methodology utilizes predictive models built upon artificial neural networks (ANNs), which is capable of modeling the relationship between the high-level attributes of a design and its associated bug information. To evaluate the performance of constructed predictive model, we conduct experiments on some open source projects. Moreover, we demonstrate the usability and effectiveness of our proposed methodology via elaborating experiences from our industrial practices. Finally, discussions on the application of our methodology are presented.

关键词： computer bugs Predictive models Complexity theory Measurement Training data Training Correlation

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A Scan-Based Delay Test Method for Reduction of Overtesting

A Scan-Based Delay Test Method for Reduction of Overtesting

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Hui Liu Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper presents a scan-based delay test method, called sequential-broad-side (SeBoS), to minimize overtesting of delay test. We consider two critical reasons for overtesting which are the existence of illegal states in sequential circuits and the high IR drop caused by power dissipation during structural test. The proposed SeBoS method inserts several slow clock cycles before applying the fast clock for detecting delay faults, thus considerable illegal states can be avoided and IR drop can be reduced. Illegal states are not necessarily computed before test generation. They can be accumulated and expanded during the automatic test pattern generation (ATPG) process. The derived illegal states are then used to guide test generation for the remaining faults. Compared with previous methods, the SeBoS method can avoid more illegal states when considering the same number of time frames. Experimental results on ISCAS-89 benchmark circuits show the effectiveness of the method.

关键词： Delay Circuit testing Sequential analysis Clocks Circuit faults Automatic test pattern generation Sequential circuits Power dissipation Electrical fault detection Fault detection

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