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IEEE International Conference on Communications

作者： Navod Suraweera Norman C. Beaulieu Department of Electrical and Computer Engineering University of Alberta School of Information and Communication Engineering and Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecomunications (BUPT)

ISBN: (纸本)9781467364300

The performance of optimum combining (OC) in decode-and forward (DF) relaying in the presence of a Poisson field of interferers is analyzed. An approximation for the outage probability of the OC receiver is derived by considering the temporal correlation of the interference. Despite the randomness of the number and the locations of the interferers, the OC receiver suppresses the interference at the destination node and diversity gains are achieved, provided that the relay nodes are noise limited. For single-antenna relay nodes, the end-to-end performance is vulnerable to interference at the relay nodes which is not canceled, resulting in zero diversity gains.

关键词： DF relaying Interference Optimum combining Outage probability Poisson point processes

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A Model Analyzing Method for OWL-S Services Composition Based on High Level Petri Net

A Model Analyzing Method for OWL-S Services Composition Base...

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International Symposium on Knowledge Acquisition and Modeling, KAM

作者： Shaoran Dong Zengzhi Li State key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China Institute of Computer System Architecture and Network Xi''an Jiaotong University Xi'an China

To analyze model of Web services composition, firstly analyze and abstract dataflow and control construct in OWL-S process to build high level Petri net model, then describe Petri net in Poses++ language, at last simulate Petri net with Poses++ to check data type and deadlock and calculate service performance. The experiment shows that this model analyzing method is able to accomplish type checking and deadlock and performance analyzing.

关键词： Performance analysis Web services system recovery Data analysis Petri nets Ontologies OWL Analytical models Knowledge acquisition computer networks

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A Case Study on At-Speed Testing for a Gigahertz Microprocessor

A Case Study on At-Speed Testing for a Gigahertz Microproces...

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Da Wang Rui Li Yu Hu Huawei Li Xiaowei Li Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics Company Limited Shanghai China

This paper describes a low cost, high quality at-speed testing strategy implemented on a gigahertz microprocessor with multi-clock domains. The presented DFT method not only utilizes the internal phase-locked loops (PLLs) to provide complex test clock sequences, but also applies a hybrid scan compression structure to reduce test data volume. It is difficult and time-consuming to generate at-speed tests for a design with embedded memories and multi-clock domains. The proposed test pattern generation scheme can gain transition fault coverage of approximately 83% for this high-performance microprocessor, and the test power consumption is well controlled.

关键词： Microprocessors Circuit testing Clocks Logic testing system testing Electronic equipment testing Test pattern generators Costs Circuit faults Energy consumption

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architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File

Architecture Level Energy Modeling and Optimization for Mult...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Ge Zhang Xu Yang Yiwei Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Information and Technology University of International Relations UIR Beijing China

In modern high performance microprocessors, multi-ported register-files are commonly used and critical in both performance and energy consumption. As capability and issue width of register-file grows, its energy consumption increases rapidly. Much prior work about energy-efficient register-file design is focusing on various low levels except for architecture level. In this paper, an accurate architectural level energy model for register-file is proposed and verified, based on which some efficient and practical improvements are presented to save energy without changing the internal circuits or structure of register-file. We implemented a full-customized 64-bit width 64-entry depth physical register-file with 8 read ports and 4 write ports, whose power is as low as 20 mW, in a 1 GHz 4-issue out-of-order 64-bit MIPS microprocessor, Godson-2 [1], using 90 nm CMOS process. 56.0% of reading energy and 20.3% of writing energy can be saved.

关键词： Circuits computer architecture Energy consumption Microprocessors Registers Energy efficiency Out of order CMOS process Writing Semiconductor device modeling

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Multi-Cell Coordinated Scheduling and Power Allocation in Downlink LTE-A systems

Multi-Cell Coordinated Scheduling and Power Allocation in Do...

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IEEE Vehicular Technology Conference

作者： Jian Yu Geoffrey Ye Li Changchuan Yin Suwen Tang Xiaolong Zhu Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications School of Electrical and Computer Engineering Georgia Institute of Technology Huawei Shanghai Research Institute

ISBN: (纸本)9781479944484

In this paper, we investigate multi-cell coordinated scheduling and power allocation in downlink long term evolution advanced (LTE-A) systems, where orthogonal frequency division multiple-access (OFDMA) is used. The proposed scheme performs joint scheduling, power allocation, and modulation and coding scheme (MCS) selection to maximize the overall weighted throughput with proportional fairness. Our scheme considers the practical constraints in LTE-A systems. Since the optimization problem is a combinatorial and non-convex one and is with high complexity, low-complexity and suboptimal algorithms are proposed, which separate the scheduling and power allocation into two subproblems. Simulation results show that the proposed scheme can improve the average system throughput by 10% and the 10th percentile throughput by 15% compared with the existing scheme.

关键词： Resource management Throughput Interference Signal to noise ratio Indexes Optimization Scheduling

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High performance comparison-based sorting algorithm on many-core GPUs

High performance comparison-based sorting algorithm on many-...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Xiaochun Ye Dongrui Fan Wei Lin Nan Yuan Paolo Ienne Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

Sorting is a kernel algorithm for a wide range of applications. In this paper, we present a new algorithm, GPU-Warpsort, to perform comparison-based parallel sort on Graphics Processing Units (GPUs). It mainly consists of a bitonic sort followed by a merge sort. Our algorithm achieves high performance by efficiently mapping the sorting tasks to GPU architectures. Firstly, we take advantage of the synchronous execution of threads in a warp to eliminate the barriers in bitonic sorting network. We also provide sufficient homogeneous parallel operations for all the threads within a warp to avoid branch divergence. Furthermore, we implement the merge sort efficiently by assigning each warp independent pairs of sequences to be merged and by exploiting totally coalesced global memory accesses to eliminate the bandwidth bottleneck. Our experimental results indicate that GPU-Warpsort works well on different kinds of input distributions, and it achieves up to 30% higher performance than previous optimized comparison-based GPU sorting algorithm on input sequences with millions of elements.

关键词： Sorting High performance computing Bandwidth Parallel architectures computer architecture Kernel Application software Multicore processing Graphics processing unit

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Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power

Extended Selective Encoding of Scan Slices for Reducing Test...

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Asian Test Symposium (ATS)

作者： Jun Liu Yinhe Han Xiaowei Li School of Computer and Information Hefei University of Technology Hefei China Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding.

关键词： Encoding Circuit testing Memory Test data compression Filling Laboratories computer architecture Merging Hardware system testing

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Frequency method to study the propagation of transient fault in combinational logic

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2008年第5期20卷 605-611+617页

作者： Lei, Shaohua Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

This paper presents a frequency analysis method to analyze the propagation procedure of transient error in combinational logic. By using the Fourier transform with the input signal and the frequency feature of combination circuit, the output can be obtained after frequency-domain computing. A model is proposed in this paper to deal with the signals which drive the combinational logic gates working at nonlinear region. The frequency analysis method is able to provide higher accuracy, while significantly speeding up simulations. Experimental results prove that our approach is several orders of magnitude faster than HSPICE, under the guarantee of approximately 93% accuracy (compared to HSPICE).

关键词： LSI circuits

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Large Scale Model Enabled Semantic Communications Based on Robust Knowledge Distillation

Large Scale Model Enabled Semantic Communications Based on R...

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2024 IEEE Global Communications Conference, GLOBECOM 2024

作者： Ding, Kuiyuan Liu, Fangfang Yang, Yang Chen, Mingzhe Guo, Caili Beijing University of Posts and Telecommunications Beijing Key Laboratory of Network System Architecture and Convergence School of Information and Communication Engineering Beijing100876 China University of Miami Department of Electrical and Computer Engineering The Institute for Data Science and Computing Coral GablesFL33146 United States Beijing University of Posts and Telecommunications Beijing Laboratory of Advanced Information Networks School of Information and Communication Engineering Beijing100876 China

ISBN: (纸本)9798350351255

Large scale artificial intelligence (AI) models possess excellent capabilities in semantic representation and understanding, making them particularly well-suited for semantic encoding and decoding. However, the substantial scale of these AI models imposes unacceptable computational resources and communication delays. To address this issue, we propose a semantic communication scheme based on robust knowledge distillation (RKD-SC) for large scale model enabled semantic communications. In the considered system, a transmitter extracts the features of the source image for robust transmission and accurate image classification at the receiver. To effectively utilize the superior capability of large scale model while make the cost affordable, we first transfer knowledge from a large scale model to a smaller scale model to serve as the semantic encoder. Then, to enhance the robustness of the system against channel noise, we propose a channel-aware autoencoder (CAA) based on the Transformer architecture. Experimental results show that the encoder of proposed RKD-SC system can achieve over 93.3% of the performance of a large scale model while compressing 96.67% number of parameters. Code: https://***/echojayne/RKD-SC. © 2024 IEEE.

关键词： Channel coding

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A virtual machine-based invasion detection system for the virtual computing environment

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High Technology Letters 2006年第4期12卷 379-384页

作者：曾宇 Wang Jie Sun Ninghui Li Jun Nie Hua Research and Development Center for National Intelligence Computing System Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China

Under virtualization idea based on large-scale dismantling and sharing, the implementing of network interconnection of calculation components and storage components by loose coupling, which are tightly coupling in traditional server, achieves computing capacity, storage capacity and service capacity distri- bution according to need in application-level. Under the new server model, the segregation and protection of user space and system space as well as the security monitoring of virtual resources are the important factors of ultimate security guarantee. This article presents a large-scale and expansible distributed invasion detection system of virtual computing environment based on virtual machine. The system supports security monitoring management of global resources and provides uniform view of security attacks under virtual computing environment, thereby protecting the user applications and system security under capacity services domain.

关键词： virtual computing environment oriented virtual machine-based invasion detection system (VIDS) capacity services computing

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