Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ldquodonpsilat-carerdquo bits can be e...
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ISBN:
(纸本)9781424428205
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ldquodonpsilat-carerdquo bits can be exploited for test data compression and/or test power reduction. Prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together. In this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. Experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.
As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more perfo...
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As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more performance requirements of a Web browser, for which user experience is very important. This situation may become more urgency when on handheld devices. Some efforts like redesign a new Web browser have been made to overcome this problem. In this paper, we address this issue by optimizing the main processes of the Web browser on a state-of-the-art 64-core architecture, Godson-T, which was developed at Chinese Academy of Sciences, as multi-/many-core architecture to be the mainstream processor in the upcoming years. We start a new core to process a new tab when facing up to intensive URL requests, and we use scratch-pad memory (SPM) of each core as a local buffer to store the HTML source data to be processed to reduce off-chip memory access and exploit more data locality, otherwise, we use DTA to transfer HTML data for backup. Experiments conducted on the cycle-accurate simulator show that, starting each tab process by a new core could obtain 5.7% to 50% speedup with different number of cores used to process corresponding URL requests, with on-chip scratchpad memory of each core used to store the HTML data, more speedup could be achieved when number of cores increase. Also, as Data Transfer Agent (DTA) used to transfer the HTML data, the backup of HTML data can get 2X to 5X speedups according to different data amount.
Energy harvesting is an emerging technology to save on-grid power and reduce carbon emissions in wireless communications. Terminals can utilize renewable energy obtained from environment by energy harvesting facilitie...
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ISBN:
(纸本)9781479987610
Energy harvesting is an emerging technology to save on-grid power and reduce carbon emissions in wireless communications. Terminals can utilize renewable energy obtained from environment by energy harvesting facilities. This paper investigates user association problem under a flow-level traffic model in energy harvesting enabled heterogeneous networks. In this paper, all the base stations are equipped with energy harvesting facilities and assumed to be solely powered by renewable energy. The average traffic delay is denoted using queuing theory, and a fairness index is redefined to evaluate the level of load balancing. Then a convex optimization problem is formulated in order to reduce average traffic delay and improve load balancing level. To this end, an iterative algorithm completed by user and base station respectively is proposed. Simulation results show that the user association algorithm improves the load balancing level with limited sacrifice on average traffic delay compared with the existing delay-optimal algorithm, and enables a flexible tradeoff between the average traffic delay and load balancing.
Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized...
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ISBN:
(纸本)9781424419210
Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.
In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5...
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In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5 LX330 FPGAs, thus permitting us to map our many-core processor and peripheral devices into it. Besides the hardware, our toolkit Godson-T Studio provides the compiler, program loader, debugger and monitor to fulfil the purpose of developing, profiling and debugging, while the accuracy loss problem is settled by our novel techniques: Check-point and ILA-Check, presented in this paper. To our experience, GVE greatly reduces the verification cycle due to its high execution speed, for example, it finishes thousands of testcases in an hour, where the software-based approach takes few days to run. And by the help of the checkpoint framework, we can easily locate the faults. Because of these features, GVE makes a great contribution to the 16-tile Godson-T tape-out Project.
Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizin...
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Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution; 2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf ) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies; 3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach.
Scan is a widely used Design-for-Testability technique to improve test and diagnosis quality. Many defects may cause scan chains to fail. In this paper, an observation point oriented Deterministic Diagnostic Pattern G...
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Scan is a widely used Design-for-Testability technique to improve test and diagnosis quality. Many defects may cause scan chains to fail. In this paper, an observation point oriented Deterministic Diagnostic Pattern Generation (DDPG) method was proposed for compound defects, which tolerates the system defects during scan chain diagnosis. Instead of sensitizing multiple paths proposed in our prior work, the proposed new DDPG method directly targets as many observation points as possible to observe the loading error occurred on the targeted scan cell. Experimental results on ISCASpsila89 benchmark circuits show that the proposed DDPG method improves the effectiveness and efficiency of diagnosing compound defects, compared to our prior research.
This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. ...
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This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals.
With the rapid development of virtualization technology, virtual machine (VM) is widely used by cloud computing - the more and more popular computing paradigm. Thus, in order to guarantee the security of cloud computi...
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With the rapid development of virtualization technology, virtual machine (VM) is widely used by cloud computing - the more and more popular computing paradigm. Thus, in order to guarantee the security of cloud computing, it is necessary to securely identify the kernel of VM, the software stack running on VM and the hardware platform which VM relies on. This paper designs a system of trusted connection based on virtual machine architecture and implements a system prototype. Our system not only can securely measure and identify the kernel of VM, the software stack running on VM and the hardware platform which VM relies on, but also can realize isolations to untrusted VMs. There are three main parts in our system: trusted chain, attestation and isolation. The experiments described in this paper prove that our system ensures trusted connection of VMs and achieves isolations to untrusted VMs. The performance of our system is also analyzed and evaluated. According to the analysis results, our system is practical in terms of performance.
Graph-coloring based spectrum resource allocation scheme for relay enhanced cellular (REC) system is proposed in this paper. During the signal transmission process, each subframe is split into two equal time slots (TS...
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ISBN:
(纸本)9781479904631;9781479904631
Graph-coloring based spectrum resource allocation scheme for relay enhanced cellular (REC) system is proposed in this paper. During the signal transmission process, each subframe is split into two equal time slots (TSs). In TS1, spectrum resource allocation between base station to relay node (BS-RN) link and base station to user equipment (BS-UE) link is studied, while spectrum resources in TS2 are allocated to BS-UE link and RN-UE link. In TS1, traffic load based resource allocation scheme is applied, where the number of resources allocated to BS-RN link is according to the number of one-hop users and two-hop users. In TS2, co-channel interference is considered in the resource allocation process, which can mitigate strong interference between BS and UE, so as to achieve a higher data rate compared with conventional proportional fair (PF) resource allocation scheme. Simulation results show that the proposed scheme can obtain high average throughput as well as user fairness.
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