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Efficient optimization methodology in early-stage design of mesh-structured on-chip Power/Ground (P/G) networks

Efficient optimization methodology in early-stage design of ...

引用

ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Luo, Zu-Ying Department of Electronics Beijing Normal University Beijing 100875 China Key Laboratory of Computer System and Architecture ICT CAS Beijing 100080 China

ISBN: (纸本)1424401615

Due to decreasing supply voltages and increasing power consumption of today's VLSI chips, IR drops on on-chip power/ground (P/G) grids have to be explicitly considered during floor-planning stage in the today's physical design flow. It is therefore very important to adjust the double-mesh P/G grids in the floor-planning for efficiently minimizing the worst-case IR drop subject to limited routing resource in early-stage P/G network design of high-end chips. In this paper, we present a novel feasible methodology to efficiently optimize the problem of mesh-structured center-bumped P/G grids under given routing resources. In [11], we have proposed the approximate current distribution (ACD) simulation method and the OS_SMACD optimization approach for early-stage single-level P/G meshes]. In this work, a feasible theory is induced to directly compute the optimal solutions OS_DMACD for practical double-mesh P/G grids of high-end chips. Experimental results show that OS_DMACD matches very well with the exact counterparts inefficiently obtained with ICCG, which can leads to significant speedup in the today IR-drop aware floor-planning. © 2006 IEEE.

关键词： VLSI circuits

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A novel post-silicon debug mechanism based on Suspect Window

A novel post-silicon debug mechanism based on Suspect Window

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作者： Gao, Jianliang Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Beijing China

Bugs are becoming unavoidable in complex integrated circuit design. It is imperative to identify the bugs as soon as possible through post-silicon debug. For post-silicon debug, observability is one of the biggest challenges. Scan-based debug mechanism provides high observability by reusing scan chains. However, it is not feasible to scan dump cycle-by-cycle during program execution due to the excessive time required. In fact, it is not necessary to scan out the error-free states. In this paper, we introduce Suspect Window to cover the clock cycle in which the bug is triggered. Then, we present an efficient approach to determine the suspect window. Based on Suspect Window, we propose a novel debug mechanism to locate the bug both temporally and spatially. Since scan dumps are only taken in the suspect window with the proposed mechanism, the time required for locating the bug is greatly reduced. The approaches are evaluated using ISCAS'89 and ITC'99 benchmark circuits. The experimental results show that the proposed mechanism can significantly reduce the overall debug time compared to scan-based debug mechanism while keeping high observability. Copyright © 2010 The Institute of Electronics, Information and Communication Engineers.

关键词： Observability

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P-GAS: Parallelizing a cycle-accurate event-driven many-core processor simulator using parallel discrete event simulation 10

P-GAS: Parallelizing a cycle-accurate event-driven many-core...

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24th Annual Workshop on Principles of Advanced and Distributed Simulation, PADS 2010

作者： Lv, Huiwei Cheng, Yuan Bai, Lu Chen, Mingyu Fan, Dongrui Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School Chinese Academy of Sciences China

ISBN: (纸本)9781424472918

Multi-core processors are commonly available now, but most traditional computer architectural simulators still use single-thread execution. In this paper we use parallel discrete event simulation (PDES) to speedup a cycle-accurate event-driven many-core processor simulator. Evaluation against the sequential version shows that the parallelized one achieves an average speedup of 10.9× (up to 13.6×) running SPLASH-2 kernel on a 16-core host machine, with cycle counter differences of less than 0.1%. Moreover, super-linear speedups are achieved between running 1 thread and 8 threads due to reduced overhead of insert-event-to-queue time and increased cache size in parallel processing. We conclude that PDES could be an attractive option for achieving fast cycle-accurate many-core processor simulations. © 2010 IEEE.

关键词： Simulators

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Beyond green: Evolution to adaptability and recyclability

Beyond green: Evolution to adaptability and recyclability

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2011 IEEE/ACM International Conference on Green Computing and Communications, GreenCom 2011

作者： Sun, Yuzhong Song, Ying Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769544663

In current social computing system, not only hardware but also software experiences a directly discarded mode. Such directly discarded mode may result in huge waste. The major challenge in green computing is the recyclability of the computing system. In order to address this challenge in the software field, this paper proposes a design idea of green software embodying the adaptability and recyclability. The adaptable and recyclable strategy may consist of two phases. The first one is compressing the increasingly deeper software stack;another one is keeping the functionality recycling and code reuse. The adaptability and recyclability mean automatically decomposing the complex software into several parts which are ease to be reused and automatically selecting the feasible parts for the on-writing software. And we also explore the system software design path to adaptability and recyclability in our previous work as well as in the future. © 2011 IEEE.

关键词： Software design

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Software and hardware co-designed multi-level TLBs for chip multiprocessors

Software and hardware co-designed multi-level TLBs for chip ...

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11th IEEE International Conference on computer and Information Technology, CIT 2011 and 11th IEEE International Conference on Scalable Computing and Communications, SCALCOM 2011

作者： Zhang, Xiaohui Cong, Ming Chen, Guangqiang Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University Beijing China National University of Defense Technology Changsha China

ISBN: (纸本)9780769543888

Translation Lookaside Buffers ( TLBs ) have a significant impact on system performance. Numerous prior studies focus on TLBs design for uniprocessors. With the advent of chip multiprocessors (CMPs), we need a shift to TLBs for chip multiprocessors. This paper presents a software-implemented level-two TLB-SL2-TLB which is a shared level-two TLB for multiprocessors. It not only reduces the cost of TLB refill handler for every processor core, but also reduces the redundant TLB misses' cost for CMPs effectively. Today, CMPs typically employ private per-core TLBs. SL2-TLB together with the hardware TLBs make up a software-hardware co-designed multilevel TLB system which brings great benefit to system performance while avoiding changing the hardware TLB. So it is a convenient and efficient method for CMPs' TLB performance improvement. The benefit brought by SL2-TLB to SPECCPU2000 is less than that to SPECCPU2006, about 5% and 7% separately. Thereinto, the average performance improvement of SPECint 2006 reaches about 12.7%. That is because the overhead for TLB refill is small when the cache is large enough to avoid a miss as walking the page table of applications with small memory footprints. The further optimization for SL2-TLB is kept the SL2-TLB table stay in L2 cache forever by the cache locking scheme. SL2-TLB together with cache locking scheme improves the performances by over 13% for SPECint 2006. And an average performance improvement of over 7% is brought to the new emerging parallel benchmark suite- Princeton Application Repository for Shared-Memory computers (PARSEC). And all the above evaluations are done on Godson-3 processors which is the latest generation of China's most powerful microprocessor family. © 2011 IEEE.

关键词： Benchmarking

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An accurate energy model for wsn node and its optimal design

An accurate energy model for wsn node and its optimal design

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ICCCAS 2007 - International Conference on Communications, Circuits and systems 2007

作者： Kan, Baoqiang Li, Cai Zhao, Lei College of Science Air Force Engineering University Xi'an China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424414741

Different from the traditional wireless networks, in wireless sensor networks(WSNs), power consumption is a critical aspect, because current nodes are always supported by constrainedenergy battery. A particular challenge in maintaining extended battery lifetime lies in achieving communications with low power. For better understanding of the design trade offs of WSNs, a more accurate power consumption model for wireless sensor node is proposed. Different from models ever showed, in which the power consumption of each component in WSN node was assumed constant, the new one takes into account energy dissipation of circuits in practical physical layer. It shows that there are some parameters such as data rate, carrier frequency, RF output power et al, which have a significant effect on the WSN node with the metric energy per useful bit (EPUB). Then an optimal design method to make the network energy efficient is described by adjusting one or more of these parameters. The efficiency of the strategy was validated by mathematical analysis and simulations. The results showed that the EPUB can be reduced by optimally choosing the ratepower combination based on the proposed power consumption model for a given load. © 2007 IEEE.

关键词： Electric power utilization

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TMemCanal: A VM-oblivious dynamic memory optimization scheme for virtual machines in cloud computing

TMemCanal: A VM-oblivious dynamic memory optimization scheme...

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10th IEEE International Conference on computer and Information Technology, CIT-2010, 7th IEEE International Conference on Embedded Software and systems, ICESS-2010, 10th IEEE Int. Conf. Scalable Computing and Communications, ScalCom-2010

作者： Li, Yaqiong Huang, Yongbing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate University Chinese of Academy of Sciences China

ISBN: (纸本)9780769541082

In current virtualized cloud platforms, resource provisioning strategy is still a big challenge. Provisioning will gain low resource utilization based on peak workload, and provisioning based on average work loads will sacrifice the potential revenue of cloud customers because of bad user experiences. VM-based performance isolation also restrains resource flowing on demand. As to memory, this eventually results in under-loaded memory and over-loaded memory in the same data center. This paper proposes a VM-oblivious dynamic memory optimization scheme, TMemCanal, which leverages under-loaded memory in a data center to accommodate the needs of loaded memory dynamically in a transparent fashion. TMemCanal is able to identify the under-loaded memory located in different VMs and reuse it in a way of memory flowing without any modification to their Guest OSs. We implemented TMemCanal through extending Xen hypervisor and evaluated using SpecWeb 2005 and LinkPack Benchmarks. Our evaluation shows that TMemCanal can efficiently save memory up to 50% with an overhead less than 7%. Our case study of server consolidation also shows TMemCanal can promote the performance of memory-intensive services up to 400%. © 2010 IEEE.

关键词： Virtual machine

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BTMD: A framework of binary translation based malcode detector

BTMD: A framework of binary translation based malcode detect...

引用

4th International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC 2012

作者： Shan, Zheng Guo, Haoran Pang, Jianmin Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China National Digital Switching System Engineering and Technology Research Center Zhengzhou China

ISBN: (纸本)9780769548104

Binary Translation technology is used to convert binary code of one Instruction Set architecture (ISA) into another. This technology can solve the software-inheritance problem and ISA-compatibility between different computers architecture. In this paper, we describe BTMD (Binary Translation based Malcode Detector), a novel framework that exploits static and dynamic binary translation features to detect broad spectrum malware and prevent its execution. By operating directly on binary code with MD Rules on the availability of source code, BTMD is appropriate for translating low-level binary code to high-level proper representation, obtaining CFG (Control Flow Graph) and other high-level Control Structure by MD Parser. Then Critical API Graph based on CFG is generated to do sub graph matching with the defined Malware Behavior Template. MD Engine in BTMD is called to undertake the process to take on the remaining code analysis. Compared with other detection approaches, BTMD is found to be very efficient in terms of detection capability and false alarm rate. © 2012 IEEE.

关键词： Binary codes

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Profile guided optimization for dataflow predication

Profile guided optimization for dataflow predication

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13th IEEE Asia-Pacific computer systems architecture Conference, ACSAC 2008

作者： Li, Wang Hong, An Yongqing, Ren Yaobin, Wang Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9781424426836

Dataflow predication provides a lightweight full support for predicated execution in dataflow-like architectures. One of its major overhead is the large amounts of fanout trees for distributing predicates to all dependant instructions. Conventional optimizations are predicating only the heads or tails of dataflow chains. Predicating tails offers more speculation but leads to resource contentions and power consumption increasing. Predicating heads is power efficient but reduces speculation and instruction level parallelism. This paper introduces a profile guided technique to combine these optimizations. It uses profiling feedback to guide the compiler in deciding to predicate at the head or tail. By predicating tails on hot paths and predicating heads on infrequent paths, this technique can get performance, power and resource efficiency Performance evaluation result shows that profile guided optimization performs better in removing fanout trees. It has 10.6% speedup over always predicating heads and 2.5% speedup over always predicating tails in performance. © 2008 IEEE.

关键词： Forestry

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CuHMMer: A load-balanced CPU-GPU cooperative bioinformatics application

CuHMMer: A load-balanced CPU-GPU cooperative bioinformatics ...

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2010 International Conference on High Performance Computing and Simulation, HPCS 2010

作者： Yao, Ping An, Hong Xu, Mu Liu, Gu Li, Xiaoqiang Wang, Yaobin Han, Wenting School of Computer Science and Technology University of Science and Technology of China Hefei 230027 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9781424468287

GPUs have recently been used to accelerate data-parallel applications for they provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power. Most of those applications use CPU as a controller who decides when GPUs run the computing-intensive tasks. This CPU-control-GPU-compute pattern wastes much of CPU's computational power. In this paper, we present a new CPU-GPU cooperative pattern for bioinformatics applications which can use both of CPU and GPU to compute. This pattern includes two parts: 1) the load-balanced data structure which manages data to keep the computational efficiency of GPU high enough when the length distribution of sequences in a sequence database is very uneven;2) multi-threaded code partition which schedules computing on CPU and GPU in a cooperative way. Using this pattern, we develop CuHMMer based on HMMER which is one of the most important algorithms in bioinformatics. The experimental result demonstrates that CuHMMer get 13x to 45x speed up over available CPU implementations and could also outperform the traditional CUDA implementations which use CPU-control-GPU-compute pattern. ©2010 IEEE.

关键词： Graphics processing unit

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