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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Zijian He Tao Lv Xiaowei Li Huawei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academ Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academ

In this paper, we focus on generation of a universal path candidate set V that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation, targeting the reduction of sensitization criteria checking times. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth first search approach.

关键词： delay testing testable long paths

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On-the-fly Reduction of Stimuli for Functional Verification

On-the-fly Reduction of Stimuli for Functional Verification

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Qi Guo Weiwu Hu Tianshi Chen Haihua Shen Yunji Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

As a primary method for functional verification of microprocessors, simulation-based verification has received extensive studies over the last decade. Most investigations have been dedicated to the generation of stimuli (test cases), while relatively few has focused on explicitly reducing the redundant stimuli among the generated ones. In this paper, we propose an on-the-fly approach for reducing the stimuli redundancy based on machine learning techniques, which can learn from new knowledge in every cycle of simulation-based verification. Our approach can be easily embedded in traditional framework of simulation-based functional verification, and the experiments on an industrial microprocessor have validated that the approach is effective and efficient.

关键词： Functional Verification Stimuli Reduction Redundancy Online Learning Godson-2

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Software-Based Self-Testing of Processors Using Expanded Instructions

Software-Based Self-Testing of Processors Using Expanded Ins...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Ying Zhang Xiaowei Li Huawei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

In this paper, an automatic test instruction generation (ATIG) technique using expanded instructions is presented for software-based selftesting (SBST) of processors. First, mappings between expanded instructions and signals are obtained through data mining, and they are used to impose value ranges of expanded instructions on component signals and generate instruction-level constraints. Second, virtual circuits are established based on the instruction-level constraints, and test patterns are generated for the constrained components. Third, test patterns are translated into test instructions according to the values of controlling signals and constraints for their mappings to instructions, and an SBST program is produced after assembling the test instructions. Experimental results on the Parwan processor show that the proposed ATIG technique can achieve 94.8％ stuck-at fault coverage, which is close to that of the full-scan test generation method. In addition, it can cut down 57％ test volume of the previous random pattern generation based SBST technique, while the test time reduces to one thirteenth of the previous SBST technique.

关键词： Software-Based Self-Test Automatic Test Instruction Generation Instruction-Level Constraint On-Line Test

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CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors

CREA: A Checkpoint Based Reliable Micro-architecture for Sup...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Shijian Zhang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

Conventional temporal redundant techniques to detect transient faults have resulted in considerable performance loss. One major reason for this problem is the reclamation of some critical resources, such as the instruction window and physical registers, is delayed, which degrades instruction-level parallelism. This paper proposes a novel fault- tolerant micro-architecture based on checkpoint mechanism. All occupied resources are reclaimed during the retirement stage in the first execution. Therefore, the performance overhead is mitigated evidently. Our scheme requires only small hardware cost and provides short fault detection latency.

关键词： Registers Fault detection Retirement Hardware Costs Delay Pipelines Buffer storage Redundancy Yarn

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Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic

Frequency Analysis Method for Propagation of Transient Error...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Shaohua Lei Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

The continuous development of VLSI technology is shrinking the minimal sizes to nanometer region, making circuits more susceptible to transient error. In this paper, we present a frequency analysis method to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We use the frequency feature of signal and frequency response of electrical system to analyze the propagation of transient error. Experiments show that on average, our approach provides approximately 95％ accuracy and several orders of magnitude faster with respect to HSPICE simulation.

关键词： Transient analysis Frequency estimation CMOS logic circuits Very large scale integration CMOS technology Circuit faults Combinational circuits Frequency response Signal analysis Circuit simulation

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A reconfigurable routing method for fault-tolerant mesh-based network on chip

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Journal of Information and Computational Science 2013年第1期10卷 157-165页

作者： Liu, Yanhua Ruan, Ying Lai, Zongsheng Sun, Ling Institute of Microelectronics Circuit and System East China Normal University Shanghai 200241 China Jiangsu Provincial Key Lab. of ASIC Design Nantong University Nantong 226019 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

As the semiconductor industry advances to nano-technology points, Network on Chip (NoC) components are becoming vulnerable to errors during the system operation. Consequently, fault-tolerant techniques for NoC are needed to achieve high reliability. In this paper, we present a fault-tolerant routing method to tolerate faulty routers in a two-dimension (2D) mesh-based NoC. With this method, the system can have a multi-router fault-tolerant capability and the routing path can be dynamically reconfigured to support different situations caused by faulty routers in NoC. Fault-tolerance capability and system performance of the proposed method are evaluated through analysis and simulations. Theoretical analysis and simulation results show that the proposed method can enhance the reliability of system and offer considerable fault-tolerance capability. © 2013 by Binary Information Press.

关键词： Network-on-chip

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An efficient and flexible task management for many cores

An efficient and flexible task management for many cores

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作者： Yuan, Nan Yu, Lei Fan, Dong-Rui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9783642245671

This paper presents the design and implementation of a runtime system (named "GodRunner") on Godson-T many-core processor to support task-level parallelism efficiently and flexibly. GodRunner abstracts underlying hardware resource, providing ease-of-use programming interface. A two-grade task management mechanism is proposed to support both coarse-grained and fine-grained multithreading efficiently. Two load-balanced scheduling policies are combined flexibly in GodRunner. The software-controlled task management makes GodRunner more configurable and extensible than hard-wired ones. The experiment shows that the tasking overhead in GodRunner is as small as hundreds of cycles, which is about the hundreds of times faster than the conventional Pthread based multithreading on a SMP machine. Furthermore, our approach scales well and supports fine-grained tasks as small as 20k cycles optimally. © 2011 Springer-Verlag Berlin Heidelberg.

关键词： computer architecture

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Testable critical path selection considering process variation

Testable critical path selection considering process variati...

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作者： Fu, Xiang Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academic of Science Beijing 100190 China Graduate University of Chinese Academic of Sciences Beijing 100039 China

Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testability of paths nor the statistical variation of cell delays caused by process variation is considered. This paper proposed a novel path selection method considering process variation. The circuit is firstly simplified by eliminating non-critical edges under statistical timing model, and then divided into sub-circuits, while each sub-circuit has only one prime input (PI) and one prime output (PO). Critical paths are selected only in critical sub-circuits. The concept of partially critical edges (PCEs) and completely critical edges (CCEs) are introduced to speed up the path selection procedure. Two path selection strategies are also presented to search for a testable critical path set to cover all the critical edges. The experimental results showed that the proposed circuit division approach is efficient in path number reduction, and PCEs and CCEs play an important role as a guideline during path selection. Copyright © 2010 The Institute of Electronics.

关键词： Delay circuits

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A unified online fault detection scheme via checking of stability violation 09

A unified online fault detection scheme via checking of stab...

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2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09

作者： Guihai, Yan Yinhe, Han Xiaowei, Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9783981080155

In ultra-deep submicro technology, two of the paramount reliability concerns are soft errors and device aging. Although intensive studies have been done to face the two challenges, most take them separately so far, thereby failing to reach better performance-cost tradeoffs. To support a more efficient design tradeoff, we present a new fault model, Stability Violation, derived from analysis of signal behavior. Furthermore, we propose a unified fault detection scheme - Stability Violation based Fault Detection (SVFD), by which the soft errors (both Single Event Upset and Single Event Transient), aging delay, and delay faults can be uniformly handled. SVFD can greatly facilitate soft error-resistant and aging-aware designs. SVFD is validated by conducting a set of intensive Hspice simulations targeting 65nm CMOS technology. Experimental results show that SVFD has more robust capability for fault detection than previous schemes at comparable overhead in terms of area, power, and performance. © 2009 EDAA.

关键词： Fault detection

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Green challenges to system software in data centers

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Frontiers of Materials Science 2011年第3期5卷 353-368页

作者： Yuzhong SUN Yiqiang ZHAO Ying SONG Vajun YANG Haifeng FANG Hongyong ZANG Yaqiong LI Yunwei GAO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100190 China

With the increasing demand and the wide application of high performance commodity multi-core processors, both the quantity and scale of data centers grow dramatically and they bring heavy energy consumption. Researchers and engineers have applied much effort to reducing hardware energy consumption, but software is the true consumer of power and another key in making better use of energy. system software is critical to better energy utilization, because it is not only the manager of hardware but also the bridge and platform between applications and hardware. In this paper, we summarize some trends that can affect the efficiency of data centers. Meanwhile, we investigate the causes of software inefficiency. Based on these studies, major technical challenges and corresponding possible solutions to attain green system software in programmability, scalability, efficiency and software architecture are discussed. Finally, some of our research progress on trusted energy efficient system software is briefly introduced.

关键词： green software multi-core data center,power efficient system software

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