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A routing algorithm for random error tolerance in network-on-chip

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12th International Conference on Human-computer Interaction, HCI International 2007

作者： Zhang, Lei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences 100080 Beijing China Graduate University Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9783540731092

In DSM and nanometer technology, there will present more and more new fault types, which are difficult to predict and avoid. Applying fault tolerant algorithms to achieve reliable on-chip communication is one of the most important issues of Network-on-Chip (NoC). This paper reviews the main on-chip fault tolerant communication algorithms and then proposes a new routing algorithm with end-to-end feedback. The average transmission latency, power consumption and reliability are compared with other techniques. As experiments show, the proposed algorithm has lower latency, lower power consumption compared with those of others, and it can provide high reliability. © Springer-Verlag Berlin Heidelberg 2007.

关键词： Routing algorithms

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Fetching primary and redundant instructions in turn for a fault-tolerant embedded microprocessor

Fetching primary and redundant instructions in turn for a fa...

引用

14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008

作者： Zhang, Shijian Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate School of the Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9780769534480

With the development of semiconductor technology, microprocessors become more and more susceptible to transient faults. Some proposed schemes support redundant execution of a program in a superscalar processor for fault tolerance. However, they require a huge queue to accommodate interim states, which enlarge the hardware cost significantly. This paper analyzes the effect of halving a processor's instruction fetch bandwidth on a program's performance. We find that the performance degradation resulted from halving instruction fetch bandwidth declines when instruction latency is lengthened, branch prediction accuracy deteriorates or cache miss rate increases. Since an embedded microprocessor is characterized by long instruction latency, high branch misprediction rate and cache miss rate, a fault-tolerant scheme is proposed, in which two threads fetch instructions in turn and execute in the same processor core simultaneously without any extra queue. The simulation results from eight embedded applications show that performance penalty of our solution ranges from 6.5% to 30.1%, with an average of 22.5%, which is lower than that of the other proposed schemes. The experiment also indicates that our scheme can effectively detect faults occurring in the entire pipeline with short fault detection latency and minimal hardware cost. It is well suited for our solution to realize a reliable embedded microprocessor. © 2008 IEEE.

关键词： Fault detection

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Poster: Revisiting virtual channel memory for performance and fairness on multi-core architecture 11

Poster: Revisiting virtual channel memory for performance an...

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Proceedings of the international conference on Supercomputing

作者： Chen, Licheng Huang, Yongbing Bao, Yungang Mutlu, Onur Tan, Guangming Chen, Mingyu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School of Chinese Academy of Sciences China Carnegie Mellon University United States

ISBN: (纸本)9781450301022

In modern multi-core chip architecture, the DRAM system is shared by more and more cores and high bandwidth I/O devices. This trend would make the problem of request contention and un-fairness more serious. Previous research focused on memory sche-duling mechanisms to efficiently and fairly serve memory requests generated by multiple cores. However, the performance is mod-erately improved due to the limited bank-level parallelism in preva-lent DRAM chips. Based on the observation that virtual channel memory (VCM) provides more opportunities for exploiting MLP because it has more channel buffers than banks in conventional DRAM chip, we evaluate VCM technology as an alternative to DRAM for addressing the issues of contention, unfairness and MLP. In this work we implement VCM and leverage the state of art scheduling mechanism on a multi-core architecture. The experi-mental results show that (i) VCM with 32 channels improves ho-mogeneous workloads' IPC by 2.08X on a 16-core system compared to the system with conventional DRAM chips, causing extra area cost by 0.5%, and dynamic and background power pe-nalties by only 5.8% and 0.03% respectively. (ii) For heterogene-ous workloads, VCM significantly reduces unfairness by 82.0% as well as improves the workloads' performance by 1.86X in term of system throughput. © 2011 Authors.

关键词： Dynamic random access storage

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Test cost efficiency exploration for CMT processors

Test cost efficiency exploration for CMT processors

引用

IEEE Region 10 International Conference TENCON

作者： Jia Li Yu Hu Xiaowei Li Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Chip multi-threading (CMT) is an architecture that can achieve overall high performance by exploiting high bandwidth rather than high frequency, thus reduce hardware complexity and power. Test cost of this architecture also can be reduced by efficiently utilizing its communication channel bandwidth during test. Because CMT architectures are designed low-power in nature, its testing should also be conducted under stringent power constraints. This paper discusses these above problems and proposes a cost-efficient test scheme. Experimental results show that our test scheme can achieve very short test time and low test data volume under stringent power constraints with low area overhead.

关键词： Costs Bandwidth system testing computer architecture Frequency Hardware Thermal management Power dissipation Network-on-a-chip Laboratories

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The implementation and design methodology of a quad-core version Godson-3 microprocessor

The implementation and design methodology of a quad-core ver...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： Baoxia Fan Liang Yang Zhuo Gao Feng Zhang Ru Wang Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Godson-3A is a quad-core version of Godson-3 series which is a 174 mm 2 , 425 million transistors chip fabricated using 65 nm CMOS LP/GP process technology. It can be running at 1 GHz with less than 15 W power consumption. Large scale, high frequency, low power and tight time schedule make great challenges in the chip design. To overcome these challenges, a design methodology based on ASIC combining with semi-custom (manual placement and routing using standard cells) and full-custom is adopted. This paper describes the implementation of Godson-3A microprocessor and the methodology used in the chip design.

关键词： Design methodology Microprocessors Chip scale packaging CMOS process CMOS technology Energy consumption Large-scale systems Frequency Processor scheduling Application specific integrated circuits

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Energy-Efficient Input Buffer Design using Data-Transition Oriented Model

Energy-Efficient Input Buffer Design using Data-Transition O...

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International Symposium on Integrated Circuits (ISIC)

作者： Jun Wang Kun Huang Ge Zhang Weiwu Hu Feng Zhang Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Network-on-chip (NoC) has been proved to be an efficient solution for interconnection between processor cores in chip multi-processor (CMP), which will consume extra energy. This paper is focusing on the energy-efficient design of input buffer, one of the most critical components in NoC. For precise calculation of energy, data-transition oriented model with multilevel simulations is proposed here. And using our method, a suit of benchmarks, SPLASH-2, are executed to evaluate the designs with different physical parameters and circuit structures. The simulations are based on 90 nm CMOS process, and the input buffer with 64-bit width and 16-entry depth is recommended for more energy-efficiency.

关键词： Energy efficiency Network-on-a-chip Energy consumption Circuit simulation Integrated circuit interconnections Bandwidth Laboratories computer networks computer architecture Content addressable storage

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Impact-factor-guided X-filling for peak power reduction during test

Impact-factor-guided X-filling for peak power reduction duri...

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IEEE Region 10 International Conference TENCON

作者： Jia Li Yu Hu Xiaowei Li Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Peak power during testing system-on-chip (SoC) circuits is a challenging issue for both reliability and yield. Because test vectors always try to activate as many faults as possible in the capture cycles, peak power during test usually happens in these cycles. X-filling is one effective way to reduce transitions happened in capture cycles to reduce peak power during test. However, its efficiency is limited and needs well exploration. This paper proposes an X impact-factor-metric to estimate the impact of filling one X bit on other X bits in test cube. This metric is utilized to efficiently guide the X-filling to reduce the capture power. We call it impact-factor-Guided (IFG) X-filling. Experimental results on larger ISCAS'89 benchmark circuits show that the average and maximum capture power can be reduced through our IFG X-filling by 65% and 31% on average, respectively.

关键词： Circuit testing Power dissipation Sequential analysis system testing CMOS technology system-on-a-chip Power system reliability Filling Reliability engineering Power engineering and energy

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Eliminating data invalidation in debugging multiple-clock chips

Eliminating data invalidation in debugging multiple-clock ch...

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作者： Gao, Jianliang Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Information Science and Engineering Central South University China

ISBN: (纸本)9783981080179

A critical concern for post-silicon debug is the need to control the chip at clock cycle level. In a single clock chip, run-stop control can be implemented by gating the clock signal using a stop signal. However, data invalidation might occur when it comes to multiple-clock chips. In this paper, we analyze the possible data invalidation, including data repetition and data loss, when stopping and resuming a multiple-clock chip. Furthermore, we propose an efficient solution to eliminate data repetition and data loss. Theoretical analysis and simulation experiments are both conducted for the proposed solution. We implement the proposed Design-for-Debug (DfD) circuit with SMIC 0.18/Ltm technology and simulate the data transfer across clock domains using SPICE tool. The results show that both data repetition and data loss can be avoided with the proposed solution, even if metastability occurs. © 2011 EDAA.

关键词： Clocks

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T2- TAM:Reusing infrastructure resource to provide parallel testing for NoC based Chip

T2- TAM:Reusing infrastructure resource to provide parallel ...

引用

International Conference on ASIC

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Beijing

Reusing network-on-chip (NoC) as test-access-mechanism (TAM) has been adopted to transfer test data to embedded cores. However, an observation shows that compared to NoC-reuse TAM, some bus-based TAM are able to achieve better results in test time due to its fine-grained scheduling unit. This paper proposed a new TAM named Test Tree(T 2 ). T 2 TAM could be built by reusing the hardware resources of routers instead of reusing the packet-based NoC. Though implementing DFT design on routers, the T2TAM can achieve wire utilization and adopts fine-grained basic scheduling. Besides, to address the problem of testing large number of homogeneous cores, T 2 -TAM is proposed to facilitate multicasting stimuli to homogeneous cores to save test time. Experimental results show that the test cycles could be reduced up to 38% in comparison with the work reusing NoC as TAM with only 0.3% DFT overhead.

关键词： Testing Network-on-a-chip Wires Rails Scheduling algorithm Hardware Design for testability Tail Payloads Protocols

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An ultra-fast hybrid simulation framework for ASIP

An ultra-fast hybrid simulation framework for ASIP

引用

2011 18th IEEE International Conference on Electronics, Circuits and systems, ICECS 2011

作者： Qiu, Ji Gao, Xiang Jiang, Yifei Xiao, Xu Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Science Beijing 100190 China Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana IL United States

ISBN: (纸本)9781457718458

ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the state-of-art dynamic binary translation simulator and is the fastest to the best of our knowledge. © 2011 IEEE.

关键词： Software design

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