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检索条件"机构=Key Laboratory of Computer System and Architecture "

共 402 条记录，以下是131-140 订阅

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A case study of improving at-speed testing coverage of a gigahertz microprocessor

A case study of improving at-speed testing coverage of a gig...

引用

2009 16th IEEE International Conference on Electronics, Circuits and systems, ICECS 2009

作者： Qi, Zichu Liu, Hui Li, Xiangku Xu, Jun Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences PO Box 2704-25 Beijing 100190 China Beijing China Loongson Technologies Corporation Limited China

ISBN: (纸本)9781424450916

For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (Random Access Memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing X states for registers, sequential bypass of macros, clock control scheme for inter-clock domains and accurate analysis of exception paths in intra-clock domains. Functional patterns are utilized to further improv. The efficiency oy the at-speed testing. A novel optimal flow is presented by carefully selecting these techniques. By usin. The flow, 90% transition fault coverage is achieved. In addition, bot. The number of patterns an. The test time oy the transition test are decreased by 15%. The total area overhead is about a few hundreds of AND cells and has little timing impact oy the critical paths. © 2009 IEEE.

关键词： Random access storage

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HPPNetSim: A parallel simulation of large-scale interconnection networks

HPPNetSim: A parallel simulation of large-scale interconnect...

引用

42nd Annual Simulation Symposium 2009, ANSS 2009, Part of the 2009 Spring Simulation Multiconference

作者： Cao, Zheng Xu, Jianwei Chen, Mingyu Zheng, Gui Lv, Huiwei Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781617386404

As the scale of parallel machine grows, communication network is playing more important role than ever before. Communication affects not only execution time, but also scalability of parallel applications. Parallel interconnection network simulator is a suitable tool to study large-scale interconnection networks. However, simulating packet level communication on detailed cycle-to-cycle network models is a really challenge work. We implement a kernel-based parallel simulator HPPNetSim to solve problems. Optimistic PDES mechanism needs huge memory consumption of saving simulation entities' states in large-scale simulations, so we chose conservative synchronization approach. Simulation kernel and network models are all carefully designed. To accelerate process of simulation, optimizations are introduced, such as block/unblock synchronization, load balancing, dynamic look-ahead generation, and etc. Simulation examples and performance results show that both high accuracy and good performance are obtained in HPPNetSim. It achieves speedup of 19.8 for 32 processing nodes when simulating 36-port 3-tree fat-tree network.

关键词： Discrete event simulation

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A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks

A Lightweight Scheme for Trust Relationship Establishment in...

引用

International Conference on computer and Information Technology (CIT)

作者： Lei Xie Yongjun Xu Xiaowei Li Yuefei Zhu Institute of Information Engineering Information and Engineering University Zhengzhou China Advanced Test Technology Laboratory Key Laboratory of Computer System and Architecture Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Ubiquitous sensor networks are application oriented system, which are composed of a large number of cooperative sensor nodes. The identification of individual sensor node is important especially for some security-sensitive applications. In this paper, we focus on the establishment of trust relationship among wireless sensor nodes, and try to combine the message authentication and identity authentication as a countermeasure to hostile attack. Accompanied with a simple lightweight key pre-distribution algorithm, in which each node sends only one message, we propose a lightweight trust relationship establishing scheme for ubiquitous sensor networks. The new scheme, which works without a trusted authority in the network, is not only concise in format but effective in practice to ensure network trusted and secure.

关键词： Authentication Protocols Pervasive computing Wireless sensor networks Information security Sensor systems and applications computer networks Ubiquitous computing Base stations Laboratories

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VMGuard: An integrity monitoring system for management virtual machines

VMGuard: An integrity monitoring system for management virtu...

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16th IEEE International Conference on Parallel and Distributed systems, ICPADS 2010

作者： Fang, Haifeng Zhao, Yiqiang Zang, Hongyong Huang, H. Howie Song, Ying Sun, Yuzhong Liu, Zhiyong Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China George Washington University WA United States

ISBN: (纸本)9780769543079

A cloud computing provider can dynamically allocate virtual machines (VM) based on the needs of the customers, while maintaining the privileged access to the Management Virtual Machine that directly manages the hardware and supports the guest VMs. The customers must trust the cloud providers to protect the confidentiality and integrity of their applications and data. However, as the VMs from different customers are running on the same host, an attack to the management virtual machine will easily lead to the compromise of the guest VMs. Therefore, it is critical for a cloud computing system to ensure the trustworthiness of management VMs. To this end, we propose VMGuard, an integrity monitoring and detecting system for management virtual machines in a distributed environment. VMGuard utilizes a special VM, Guard Domain, which runs on each physical node to monitor the co-resident management VMs. The integrity measurements collected by the Guard Domains are sent to the VMGuard server for safe store and independent analysis. The experimental evaluation of a Xen-based prototype shows that VMGuard can quickly detect the root kit attacks while the performance overhead is low. © 2010 IEEE.

关键词： Virtual machine

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HPPNetSim: A parallel simulation of large-scale interconnection networks

HPPNetSim: A parallel simulation of large-scale interconnect...

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2009 Spring Simulation Multiconference, SpringSim 2009

作者： Cao, Zheng Xu, Jianwei Chen, Mingyu Gui, Zheng Lv, Huiwei Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

As the scale of parallel machine grows, communication network is playing more important role than ever before. Communication affects not only execution time, but also scalability of parallel applications. Parallel interconnection network simulator is a suitable tool to study large-scale in-terconnection networks. However, simulating packet level communication on detailed cycle-to-cycle network models is a really challenge work. We implement a kernel-based parallel simulator HPPNetSim to solve problems. Optimistic PDES mechanism needs huge memory consumption of sav-ing simulation entities' states in large-scale simulations, so we chose conservative synchronization approach. Simula-tion kernel and network models are all carefully designed. To accelerate process of simulation, optimizations are in-troduced, such as block/unblock synchronization, load balancing, dynamic look-ahead generation, and etc. Simula-tion examples and performance results show that both high accuracy and good performance are obtained in HPPNetSim. It achieves speedup of 19.8 for 32 processing nodes when simulating 36-port 3-tree fat-tree network.

关键词： Discrete event simulation

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Cross-layer optimized placement and routing for FPGA soft error mitigation

Cross-layer optimized placement and routing for FPGA soft er...

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作者： Huang, Keheng Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. Our analysis shows that the statistical variation of the application level factor is significant. Hence in this work, we first propose a cube-based analysis to efficiently and accurately evaluate the application level factor. And then we propose a cross-layer optimized placement and routing algorithm to reduce the SER by incorporating the application level and the physical level factor together. Experimental results show that, the average difference of the application level factor between our cube-based method and Monte Carlo golden simulation is less than 0.01. Moreover, compared with the baseline VPR placement and routing technique, the cross-layer optimized placement and routing algorithm can reduce the SER by 14% with no area and performance overhead. © 2011 EDAA.

关键词： Field programmable gate arrays (FPGA)

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On capture power-aware test data compression for scan-based testing

On capture power-aware test data compression for scan-based ...

引用

2008 International Conference on computer-Aided Design, ICCAD

作者： Li, Jia Liu, Xiao Zhang, Yubin Hu, Yu Li, Xiaowei Xu, Qiang Key Laboratory of Computer System and Architecture ICT CAS Beijing China Graduate University Chinese Academy of Sciences Beijing China Deptartment of Computer Science and Engineering Chinese University of Hong Kong Shatin N.T. Hong Kong

ISBN: (纸本)9781424428205

Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the "don't-care" bits can be exploited for test data compression and/or test power reduction. Prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together. In this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. Experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.

关键词： Power management

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On diagnosis of multiple faults using compacted responses

On diagnosis of multiple faults using compacted responses

引用

作者： Ye, Jing Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

With the exponential growth in the number of transistors, not only test data volume and test application time may increase, but also multiple faults may exist in one chip. Test compaction has been a de-facto design-for-testability technique to reduce the test cost. However, the compacted test responses make multiple-fault diagnosis rather difficult. When there is no space compactor, the most likely suspect fault is considered producing the failing responses most similar to the failing responses observed from the automatic test equipment. But when compactor exists, those suspect faults may no longer have the same high possibility of being the actual faults. To address this problem, we introduce a novel metric explanation necessity. By using both of the new metric and the traditional metric explanation capability, we evaluate the possibility of a suspect fault to be the actual fault. For ISCAS'89 and ITC'99 benchmark circuits equipped with extreme space compactors, experimental results show that 98.8% of the top-ranked suspect faults hit the actual faults, outperforming a previous work by 11.3%. © 2011 EDAA.

关键词： Design for testability

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A cost-effective substantial-impact-filter based method to tolerate voltage emergencies

A cost-effective substantial-impact-filter based method to t...

引用

作者： Pan, Songjun Hu, Yu Hu, Xing Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution;2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies;3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach. © 2011 EDAA.

关键词： Cost effectiveness

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Improve accuracy of delay element by filtering false path for low power desychronized circuits

Improve accuracy of delay element by filtering false path fo...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Jun Xu Xiangku Li Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China

Desynchronized circuits outperform the synchronous counterparts in power, performance, robustness according to many studies, and delay elements are important components by mimicking the critical path delay of two arbitrary correlated latches to act as completion detection logic. In classical design flow, the critical path delay is derived through static timing analysis (STA); however, this approach may cause conservative results since STA can not identify false paths which are never activated in real life. In this paper, we firstly prove that existence of false path is a common phenomenon by making an experiment on ISCAS89 benchmarks, and then propose a fast and easy filtering method by utilizing ATPG technique. A case study on an industrial design block shows its effectiveness in improving performance, area and power.

关键词： Delay Asynchronous circuits Optimization Automatic test pattern generation Filtering Synchronization

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