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检索条件"机构=Key Laboratory of Computer System and Architecture "

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A Case Study: Low Power Design-for-Testability Features of a Multi-core Processor Godson-T

A Case Study: Low Power Design-for-Testability Features of a...

引用

2011 2nd International Conference on Advanced Measurement and Test (AMT 2011)

作者： Da Wang Dongrui Fan Yu Hu Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical coresSince the silicon design technology scales to ultra deep submicron and even nanometers, the complexity and cost of testing is growing up, and the test power of such designs is extremely curious, especially for multicore processorsIn this paper, we use the modular design methodology and scaleable design-for-testability(DFT) structure to achieve low test power, at the same time, an improved test pattern generation method is studied to reduce test power further moreThe experimental results from the real chip show that the test power and test time are well balanced while achieving acceptable test coverage and cost.

关键词： design-for-testability(DFT),multi-core processor,very large scale integration(VLSI),power reduction,pattern filling,multi-capture

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A New Post-Silicon Debug Approach Based on Suspect Window

A New Post-Silicon Debug Approach Based on Suspect Window

引用

IEEE VLSI Test Symposium (VTS)

作者： Jianliang Gao Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781424437696

Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. Then we introduce "suspect window" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain. Since scan dumps take place only in suspect window, debug time is greatly reduced. Experimental results demonstrate the effectiveness of the proposed approach.

关键词： Post-silicon debug Suspect window Trace Scan Bug

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Protein structure superposition by curve moment invariants and iterative closest point

Protein structure superposition by curve moment invariants a...

引用

2007 1st International Conference on Bioinformatics and Biomedical Engineering, ICBBE

作者： Xu, Dong Li, Hua Gu, Tongjun Key Laboratory of Intelligent Information Processing Key Laboratory of Computer System and Architecture National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Center for Systems Biology Institute of Biophysics Chinese Academy of Sciences Graduate University Chinese Academy of Sciences

ISBN: (纸本)1424411203

Superimpose one protein tertiary structure to another can help to find similarity between them and further identify functional and evolutionary relationships. We first extract invariant features under rigid body transformation for each protein backbone which is represented by alpha-carbons of all the residues. Then, the invariant features are embedded with Iterative Closest Point algorithm for superposition. With several initialized orientations, pairwise alignment can be achieved accurately only by few iterations. Experiments indicate that our proposed algorithm is competitive with several well-known algorithms and with smallest root mean squared distance. © 2007 IEEE.

关键词： Proteins

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Building a personal high performance computer with heterogeneous processors

Building a personal high performance computer with heterogen...

引用

International Conference on Grid and Cloud Computing

作者： Li, Qiang Huo, Zhigang Sun, Ninghui National Research Center for Intelligent Computing Systems Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9780769543130

Personal high performance computer (PHPC) requires lower cost and high performance. The Teraflops PHPC systems with special accelerator units like GPGPU have been presented, but they have difficulties in programming, compatibility and applicability. In this paper, we present HPP-PHPC, a hybrid architecture of heterogeneous processors connected by non-coherent off-chip system bus. The performance of HPP-PHPC is ensured by special processors integrated with vector units and high-efficiency interconnection between heterogeneous processors. And by the adoption of general processors and features like global physical address space and synchronization semantics in hardware, HPP-PHPC is more compatible and convenient for massage passing and PGAS programming model. Also it is more applicable to most applications, including those with many execution branches. Initial results obtained from our prototype system have proved our design. © 2010 IEEE.

关键词： Semantics

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A testability-aware low power architecture

A testability-aware low power architecture

引用

25th IEEE International system-on-Chip Conference, SOCC 2012

作者： Wang, Gang Wang, Jian Qi, Zi-Chu Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China

ISBN: (纸本)9781467312950

Test power consumption is becoming a major concern in low power integrated circuits(ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption. © 2012 IEEE.

关键词： Electric power utilization

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A processor-DMA-based memory copy hardware accelerator

A processor-DMA-based memory copy hardware accelerator

引用

IEEE International Conference on Networking, architecture and Storage

作者： Su, Wen Wang, Ling Su, Menghao Liu, Su Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769545097

For many Operating systems and device drivers, memory copy is the most time-consuming operation which has always been paid special attention. In this paper, we propose a processor DMA based memory copy hardware accelerator with the goal to reduce the instructions executed on CPU, and exploit the parallelism between computing and data transfer in memory copy. This is accomplished by taking advantage of a proposed Direct Memory Access (DMA) engine in the processor which overcomes many conventional DMA engine shortcomings. Experimental results show that the proposed hardware solution achieves a speedup of 14.79 compared with the optimized software solution and an overlap of 81.8% in computing and data transfer on average. © 2011 IEEE.

关键词： Engines

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Cache locking for network processing acceleration

Cache locking for network processing acceleration

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2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

作者： Su, Wen Gao, Xiang Wang, Jing You, Ruibang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China Graduate University Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769547015

With the dramatic increase in network speed during the past ten years, network processing efficiency has been significantly decreased. In this paper, we propose a network accelerating scheme, which employs cache locking method to reduce data and instruction accessing latency. Interrupts handling and buffer maintenance overheads are obviously decreased. Experimental results show that our solution increases about 22% network bandwidth and reduces 10% latency. © 2012 IEEE.

关键词： Locks (fasteners)

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Simplified Multi-Ported Cache in High Performance Processor

Simplified Multi-Ported Cache in High Performance Processor

引用

International Conference on Networking, architecture, and Storage (NAS)

作者： Hao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

The memory bandwidth demands of modern microprocessors require the use of a multi-ported cache to achieve peak performance. However, multi- ported caches are costly to implement. In this paper we propose technique for using a simplified dual-ported cache instead, which is mostly composed of single- ported SRAMs, without decreasing the performance of the processor apparently. We evaluate this technique using realistic applications that include the operating system. Our technique using a simplified multi-ported banking cache, reduces the delay of select logic in LSQ by 16.1%, and achieves 98.1% of the performance of an ideal dual-ported cache.

关键词： Microprocessors Costs Delay Bandwidth Banking Clocks Laboratories High performance computing computer architecture Operating systems

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Efficient Optimization Methodology in Early-Stage Design of Mesh-structured On-Chip Power/Ground(P/G) Networks

Efficient Optimization Methodology in Early-Stage Design of ...

引用

2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Zu-ying Luo Department of Electronics Beijing Normal University Key Laboratory of Computer System and Architecture ICTCAS

ISBN: (纸本)1424401607

Due to decreasing supply voltages and increasing power consumption of today’s VLSI chips,IR drops on on-chip power/ground(P/G) grids have to be explicitly considered during floor-planning stage in the today’s physical design flow. It is therefore very important to adjust the double-mesh P/G grids in the floor-planning for efficiently minimizing the worst-case IR drop subject to limited routing resource in early-stage P/G network design of high-end *** this paper, we present a novel feasible methodology to efficiently optimize the problem of mesh-structured center-bumped P/G grids under given routing ***[11],we have proposed the approximate current distribution(ACD) simulation method and the OSMACD optimization approach for early-stage single-level P/G meshes].In this work,a feasible theory is induced to directly compute the optimal solutions OSMACD for practical double-mesh P/G grids of high-end *** results show that OS DMACD matches very well with the exact counterparts inefficiently obtained with ICCG,which can leads to significant speedup in the today IR-drop aware floor-planning.

关键词： picogram Floor plans Power consumption grids Grates system-on-chip computer chips iridium

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Optimizing Parallel Kinetic Monte Carlo Simulation by Communication Aggregation and Scheduling

Optimizing Parallel Kinetic Monte Carlo Simulation by Commun...

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2015大数据技术及应用论坛

作者： Baodong Wu Shigang Li Yunquan Zhang State Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Kinetic Monte Carlo(KMC) algorithm has been widely applied for simulation of radiation damage, grain growth and chemical reactions. To simulate at a large temporal and spatial scale, domain decomposition is commonly used to parallelize the KMC algorithm. However, through experimental analysis, we find that the communication overhead is the main bottleneck which affects the overall performance and limits the scalability of parallel KMC algorithm on large-scale clusters. To alleviate the above problems, we present a communication aggrega‐tion approach to reduce the total number of messages and eliminate the commu‐nication redundancy, and further utilize neighborhood collective operations to optimize the communication scheduling. Experimental results show that the opti‐mized KMC algorithm exhibits better performance and scalability compared with the well-known open-source library—SPPARKS. On 32-node Xeon E5-2680 cluster(total 640 cores), the optimized algorithm reduces the total execution time by 16 %, reduces the communication time by 50 % on average, and achieves 24 times speedup over the single node(20 cores) execution.

关键词： Domain decomposition Communication aggregation Communication scheduling Neighborhood collectives

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