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检索条件"机构=Key Laboratory of Computer System and Architecture "

共 402 条记录，以下是151-160 订阅

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Design and Implementation of Floating Point Stack on General RISC architecture

Design and Implementation of Floating Point Stack on General...

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Euromicro Conference on Parallel, Distributed and Network-Based Processing

作者： Xuehai Qian He Huang Hao Zhang Guoping Long Junchao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

This paper presents a framework for implementing the X86 FP stack used in an x86-compliant processor based on a general RISC architecture. Architectural supports are added to a typical RISC architecture to maintain the FP stack status. Some speculative techniques are applied to the decode stage to enable pipelined and efficient FP operations. An optimized register renaming scheme is proposed to eliminate redundant micro-ops in FP programs, resulting in an increased performance while mitigating the burden on register rename table. The simulation results show that on average more than 10% fmov micro-ops are removed. Elimination of micro-ops significantly speeds up the execution of programs. The IPC increases are as high as 30% for some programs, and near 10% on average

关键词： Reduced instruction set computing Registers computer architecture Decoding Helium Laboratories Design methodology Prototypes Analytical models Performance analysis

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DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance

DMA cache: Using on-chip storage to architecturally separate...

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IEEE Symposium on High-Performance computer architecture

作者： Dan Tang Yungang Bao Weiwu Hu Mingyu Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

ISBN: (纸本)9781424456581

As technology advances both in increasing bandwidth and in reducing latency for I/O buses and devices, moving I/O data in/out memory has become critical. In this paper, we have observed the different characteristics of I/O and CPU memory reference behavior, and found the potential benefits of separating I/O data from CPU data. We propose a DMA cache technique to store I/O data in dedicated on-chip storage and present two DMA cache designs. The first design, Decoupled DMA Cache (DDC), adopts additional on-chip storage as the DMA cache to buffer I/O data. The second design, Partition-Based DMA Cache (PBDC), does not require additional on-chip storage, but can dynamically use some ways of the processor's last level cache (LLC) as the DMA cache. We have implemented and evaluated the two DMA cache designs by using an FPGA-based emulation platform and the memory reference traces of real-world applications. Experimental results show that, compared with the existing snooping-cache scheme, DDC can reduce memory access latency (in bus cycles) by 34.8% on average (up to 58.4%), while PBDC can achieve about 80% of DDC's performance improvements despite no additional on-chip storage.

关键词： Cache storage Delay Bandwidth Buffer storage system-on-a-chip Laboratories computer architecture Emulation Throughput Hard disks

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Empirical design bugs prediction for verification

Empirical design bugs prediction for verification

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作者： Guo, Qi Chen, Tianshi Shen, Haihua Chen, Yunji Wu, Yue Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Beijing 100049 China Loongson Technologies Corporation Limited Beijing 100190 China

ISBN: (纸本)9783981080179

Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is to expose as many bugs as possible. In this paper, we propose a novel verification methodology that leverages the early bug prediction of a DUV to guide and assess related verification process. To be specific, this methodology utilizes predictive models built upon artificial neural networks (ANNs), which is capable of modeling the relationship between the high-level attributes of a design and its associated bug information. To evaluate the performance of constructed predictive model, we conduct experiments on some open source projects. Moreover, we demonstrate the usability and effectiveness of our proposed methodology via elaborating experiences from our industrial practices. Finally, discussions on the application of our methodology are presented. © 2011 EDAA.

关键词： Neural networks

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IFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing 08

IFill: An Impact-Oriented X-Filling Method for Shift- and Ca...

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2008 Design, Automation and Test in Europe (DATE 2008), vol.3

作者： Jia LI Qiang XU Yu HU Xiaowei LI Key Laboratory of Computer System and Architecture ICT CAS Beijing China and Graduate University of Chinese Academy of Sciences Beijing China The Chinese University of Hong Kong Key Laboratory of Computer System and Architecture ICT CAS Beijing China

ISBN: (纸本)9783981080131

In scan-based tests, power consumptions in both shift and capture phases may be significantly higher than that in normal mode, which threatens circuits' reliability during manufacturing test. In this paper, by analyzing the impact of X-bits on circuit switching activities, we present an X-filling technique that can decrease both shift- and capture-power to guarantees the reliability of scan tests, called iFill. Moreover, different from prior work on X-filling for shift-power reduction which can only reduce shift-in power, iFill is able to decrease power consumptions during both shift-in and shift-out. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed technique.

关键词： scan-based testing power reduction Electric circuits Power (Psychology) Energy sources circuit switching scanning reduction

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Optimizing MPI alltoall communication of large messages in multicore clusters

Optimizing MPI alltoall communication of large messages in m...

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2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2011

作者： Li, Qiang Huo, Zhigang Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Chinese Academy of Sciences Graduate University Beijing 100049 China

ISBN: (纸本)9780769545646

MPI Alltoall communication is widely used in many high performance computing (HPC) applications. In Alltoall communication, each process sends a distinct message to all other participating processes. In multicore clusters, processes within a node simultaneously contend for the same network resource of the node in Alltoall communication. However, many small synchronization messages are required in Alltoall communication of large messages. With the contention, their latency is orders of magnitude larger than that without contention. As a result, the synchronization overhead is significantly increased and accounts for a large proportion to the whole latency of Alltoall communication. In this paper, we analyse the considerable overhead of synchronization messages. Base on the analysis, an optimization is presented to reduce the number of synchronization messages from 3N to 2√N. Evaluations on a 240-core cluster show that the performance is improved by almost constant ratio, which is mainly determined by message size and independent of system scale. The performance of Alltoall communication is improved by 25% for 32K and 64K bytes messages. For FFT application, performance is improved by 20%. © 2011 IEEE.

关键词： Synchronization

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Testing content addressable memories using instructions and march-like algorithms

Testing content addressable memories using instructions and ...

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15th IEEE International Conference on Electronics, Circuits and systems, ICECS 2008

作者： Lin, Ma Yunji, Chen Menghao, Su Zichu, Qi Heng, Zhang Weiwu, Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704-25 Beijing 100080 China Graduate University Chinese Academy of Science Beijing 100049 China

ISBN: (纸本)9781424421824

CAM is widely used in microprocessors and SOC TLB modules. It gives great advantage for software development. And TLB operations become bottleneck of the microprocessor performance. The test cost of normal BIST approach of the CAM can not be ignored. The paper analyses the fault models of CAM and proposes an instruction suitable march-like algorithm. The algorithm requires 14N+2L operations, where N is the number of words of the CAM and L is the width of a word. The algorithm covers 100% targeted faults. Instruction-level test using the algorithm has not any test cost on area and performance. Moreover the algorithm can be used in BIST approaches and have less performance lost for microprocessors. The paper instances the algorithm in a MIPS compatible microprocessor and have good results. © 2008 IEEE.

关键词： system-on-chip

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DCMTs: Supporting dynamically created migratory threads

DCMTs: Supporting dynamically created migratory threads

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International Conference on Computational Science and Engineering

作者： Zhu, Yueting Zhang, Wu Jiang, Hai Lei, Yu Peng, Junjie Department of Computer Science and Engineering Shanghai University Shanghai China Department of Computer Science Arkansas State University Jonesboro AR United States Department of Computer Science and Engineering University of Texas Arlington TX United States Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9780769543239

Thread migration is an effective technique for fault resilience and load balancing in high performance computing. However, flexible thread migration is not easy to achieve. In this paper, we present an approach to creating migratory threads dynamically at application level. The targets must be executable source files. Compared to the static ones, the number of threads created during migration with the new scheme is independent from the context. Various thread cases are considered for migration. Thread state is handled at application level. Variables are saved in structures in C language for speedy state construction. In order to solve the inability of traditional methods in tracking the created threads, a tree of active function calls is used to record the callback. The preprocessor of the proposed one is written in YACC for accuracy and programmability. The migration enabling process is transparent to programmers with the help of the preprocess. The experimental results have demonstrated the effectiveness of this approach. © 2010 IEEE.

关键词： Fault tolerance

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A differential public PUF design for lightweight authentication 16

A differential public PUF design for lightweight authenticat...

引用

2021 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2021 and 16th Conference on PhD Research in Microelectronics and Electronics, PRIME 2021

作者： Duan, Shengyu Sai, Gaole School of Computer Engineering and Science Shanghai University Shanghai200444 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Guangdong Provincial Key Lab of Robotics and Intelligent System Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences China CAS Key Laboratory of Human-Machine Intelligence-Synergy Systems Shenzhen Institutes of Advanced Technology China

ISBN: (纸本)9783800755899

Physical Unclonable Functions (PUFs) have emerged as a promising primitive to provide a hardware keyless security mechanism for integrated circuit applications. Public PUFs (PPUFs) address the crucial PUF vulnerability of requiring databases to store the secrete reference information. This paper investigates one of the PPUF families, differential PPUF (dPPUF), which exploits complexly interacted logic to create time gap between actual execution and simulation, and to prevent simulation attacks. Conventional dPPUFs have high costs. We observe the repressers have large impact on simulation time, but take a great proportion in current dPPUF structure. We thereby present a represser network with specially designed interconnection and shared logic, to maintain a high circuit complexity and to reduce the area cost. We show the proposed dPPUF has similar resilience over simulation attacks as the conventional design. Area cost can be reduced by up to 44%, and thus the proposed design can be used for lightweight authentication. © VDE VERLAG GMBH.

关键词： Authentication

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MCC: A Load Balancing and Deadlock Free Interconnect Network for Cache Coherent Chip Multiprocessors

MCC: A Load Balancing and Deadlock Free Interconnect Network...

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IEEE International Conference on Computational Science and Engineering, CSE

作者： Liwei Chen Guangfei Zhang Huandong Wang Wenxiang Wang Ling Li Hua Jing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

As the number of cores in chip multiprocessors (CMPs) increases, network-on-chip (NoC) has become a major role in ensuring performance and power scalability. In this paper, we propose multiple-combinational-channel (MCC), a load balancing and deadlock free interconnect network for cache-coherent non-uniform memory accessing (CC-NUMA). In order to make load more balancing and reduce power dissipation, we combine low usage channels and make high usage channels independent and wide enough, since messages transmitted over NoC have different widths and injection rates. Furthermore, based on the in-depth analysis of network traffic, we summarize four traffic patterns and establish several rules to avoid protocol-level deadlock. We implement MCC on a 16-core CMPs, and evaluate the power and performance using universal workloads. The experimental results show that MCC reduces nearly 21% power than multiple-physical-channel with similar throughput. Moreover, MCC improves 10% performance with similar area and power, compared to packet-switching architecture with virtual channels.

关键词： system recovery system-on-a-chip Program processors Bandwidth Load management Throughput Scalability

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Low Power Techniques on a High Speed Floating-point Adder Design

Low Power Techniques on a High Speed Floating-point Adder De...

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IEEE International Conference on Integration Technology (ICIT)

作者： Ge Zhang Kun Huang Haihua Shen Feng Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

A 64 bit low power, high speed floating-point adder design is presented in this paper. The proposed floating-point adder is based on dual path architecture, and both dynamic and leakage power are reduced by exploiting architecture opportunities to minimize switching activity and maximize the stack effect of the circuits concurrently. Experimental result based on 130 nm CMOS standard cell design shows that average power consumptions of the FP adder can be reduced by 61.4% with proposed low power techniques.

关键词： Adders Energy consumption Microprocessors Delay computer architecture Laboratories Switching circuits Central Processing Unit CMOS logic circuits Logic design

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