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Graph partition based path selection for testing of small delay defects 10

Graph partition based path selection for testing of small de...

引用

Asia and South Pacific Design Automation Conference

作者： Zijian He Tao Lv Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781605588377

Critical path selection plays an important role in testing of small delay defects (SDD). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo simulation based statistical timing analysis very inefficient. A fast path selection approach based on graph partition is proposed in this paper. First, a critical path graph (CPG) is generated to implicitly enumerate almost all candidate critical paths, and then the CPG is partitioned into several sub graphs which contain limited numbers of paths using two graph partition approaches. After that, Monte Carlo simulation is applied on each sub graph for path selection. At last, according to the partition topology of the CPG and path sets selected from each sub graph, a path set for the original CPG is generated using Union and Cartesian product operations for testing SDDs. Experimental results show that for circuits containing large numbers of candidate critical paths, the proposed path selection approach can reduce the CPU time significantly and maintain a higher probability of capturing delay failures compared to path selection methods based on general Monte Carlo simulation.

关键词： Timing Circuit testing Delay effects Sampling methods Monte Carlo methods Crosstalk system testing Laboratories Distributed computing computer architecture

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Design of NIC Based on I/O Processor for Cluster Interconnect Network

Design of NIC Based on I/O Processor for Cluster Interconnec...

引用

International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaojun Yang Dongdong Wu Ninghui Sun National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

An effective interconnect network interface card (NIC) is critical to the achievement of a high-performance cluster system. An original NIC architecture based on the Intel IOP310 I/O processor chipset is presented in this paper. The NIC is a part of DCNet, which is the cluster interconnect network developed by NCIC. The I/O processor makes it powerful for the NIC to offload the processing of communication protocol from the host CPU. In the NIC architecture, the memory bus is extended to be a local bus for system peripheral interconnection, and a memory integrated network interface (MINI) is implemented and embedded. The testing results of DCNet show that the NIC obtains reasonable user-level communication performance, and prove that the NIC architecture, which based on I/O processor and the MINI approach, is feasible and effective to achieve the high performance.

关键词： computer architecture computer networks Network interfaces Supercomputers Bandwidth Intelligent systems Intelligent networks computer interfaces Power system interconnection Protocols

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Evaluation Method of Synchronization for Shared-Memory On-Chip Many-Core Processor

Evaluation Method of Synchronization for Shared-Memory On-Ch...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Fenglong Song Zhiyong Liu Dongrui Fan He Huang Nan Yuan Lei Yu Junchao Zhang Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

On-chip many core architecture is an emerging and promising computation platform. High speed on-chip communication and abundant chipped resources are two outstanding advantages of this architecture, which provide an opportunity to implement efficient synchronization scheme. The practical execution efficiency of synchronization scheme is critical to this platform. However, there are few researches on systematic evaluation method of choice synchronization schemes for on-chip many core processors, and effect of dedicated hardware support in this context. So we focus on the evaluation method and criterion of synchronization scheme on the platform. Firstly, we present several criterions proper to on-chip many core architecture, that is, absolute overhead of synchronization operation, the transferring time between different synchronization operations, overhead caused by load imbalance, and the network congestion caused by synchronization operation. Secondly, we illustrate how to design microbenchmarks which one dedicated to evaluate a performance criterion respectively. Finally, we implement these microbenchmarks and synchronization schemes on an on-chip many core processor with shared level-two cache and AMD Opteron commercial chip multi-processor, respectively. And we analyze effect of dedicated hardware support. Results show that the most overhead of synchronization is caused by load imbalance and serialization on synchronization point. It also shows that synchronization scheme supported with dedicated hardware can improve its performance obviously for chipped many-core processor.

关键词： computer architecture Hardware Yarn Costs system-on-a-chip Concurrent computing Distributed computing Network-on-a-chip Distributed processing Application software

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A Network Memory architecture Model and Performance Analysis

A Network Memory Architecture Model and Performance Analysis

引用

International Conference on Networking, architecture, and Storage (NAS)

作者： Li Liu Mingyu Chen Yungang Bao Jianwei Xu Jianping Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

This paper presents a network memory architecture and makes a performance model to analysis the slowdown caused by the remote access delay. In this architecture the network memory is accessed through a smart network memory controller. A local page cache and a virtual page prefetching engine are designed in the smart network memory controller to improve the memory access performance.

关键词： Prefetching Delay Memory architecture Memory management computer architecture Engines Monitoring

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A case study of improving at-speed testing coverage of a gigahertz microprocessor

A case study of improving at-speed testing coverage of a gig...

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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： Zichu Qi Hui Liu Xiangku Li Jun Xu Weiwu Hu Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424450909;9781424450916

For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (random access memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing X states for registers, sequential bypass of macros, clock control scheme for inter-clock domains and accurate analysis of exception paths in intra-clock domains. Functional patterns are utilized to further improve the efficiency of the at-speed testing. A novel optimal flow is presented by carefully selecting these techniques. By using the flow, 90% transition fault coverage is achieved. In addition, both the number of patterns and the test time of the transition test are decreased by 15%. The total area overhead is about a few hundreds of AND cells and has little timing impact on the critical paths.

关键词： Microprocessors Clocks Test pattern generators system testing Costs Timing Automatic test pattern generation Delay Pattern analysis Laboratories

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A Universally Stable and Energy-Efficient Scheduling Protocol for Packet Switching Network

A Universally Stable and Energy-Efficient Scheduling Protoco...

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IEEE International Symposium on Network Computing and Applications

作者： Yangguang Shi Fa Zhang Zhiyong Liu Institute of Computing Technology Chinese Academy of Sciences China Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China

ISBN: (纸本)9781479906055

Energy efficiency is becoming an important issue in networks. Although some research works have been devoted to this topic, only a little attention has been paid to the stability of the network equipped with the energy conservation mechanisms. In fact, we find that the stability of networks can be undermined in the worst case if it isn't considered with care by the energy conservation *** this paper, we propose an energy-efficient scheduling protocol which can guarantee the stability of the network in all cases. We start by building a new model which can be used to verify the stability of the network equipped with the energy conservation mechanisms. With this model, we transform the packet scheduling problem to a Job Shop Scheduling problem. For this problem, we propose a time-stamp based work-conserving scheduling algorithm - G-FSA. Compared with existing methods, this scheduling algorithm guarantees a tighter bound on the make span of the jobs. Then, we integrate G-FSA with a time partition approach to generate our energy-efficient packet scheduling protocol. It is proved that the obtained protocol can guarantee the stability of network in all cases. And its approximation ratio in terms of energy efficiency can be bounded by O((1+∈ ) α ) for any ∈ > 0, where is an input parameter depending on the hardware infrastructure. Typically, 1

关键词： Protocols Job shop scheduling Scheduling algorithms Stability analysis Approximation methods Energy conservation

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An Efficient Shared Memory Based Virtual Communication system for Embedded SMP Cluster

An Efficient Shared Memory Based Virtual Communication Syste...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Wenxuan Yin Xiang Gao Xiaojing Zhu Deyuan Guo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Institute of Microelectronics Tsinghua University Beijing China

With the prevalence of multi-core processors, it is a trend that the embedded cluster deploys SMP nodes to gain more computing power. As a crucial issue, the MPI inter-process communication has been suffering the contradiction between high performance and embedded constraints. Moreover, there is a big performance gap between intra- and inter-node communication for different infrastructures. In this paper, we design a virtual communication system called SMVN, which extends the shared memory mechanism typically used in intra-node case into the inter-node case. The SMVN utilizes the HT inter-chip interconnect interface in Godson-3A SMP nodes to build a mesh topology. It is Ethernet compatible by simulating bottom layers of TCP/IP protocol. With the design, the node interconnection can get rid of NICs, cables and switches. Furthermore, we exploit the zero-copy scheme and other optimizations to improve the performance. We port the MPICH2 library by socket channel and formulate its process allocation. The MPI latency and bandwidth tests show that the performance difference between two levels is small. The inter-node bandwidth is 27.3 MB/s, which is more than twice the theoretical peak value of 100 Mb Ethernet and reaches 84% of the intra-node performance.

关键词： Program processors IP networks Protocols computer architecture Bandwidth Resource management Synchronization

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Static Crosstalk Noise Analysis with Transition Map

Static Crosstalk Noise Analysis with Transition Map

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Minjin Zhang Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

As the feature size scales into the nanometer era, crosstalk noise begins to exert a more significant adverse influence on circuit and need to be estimated efficiently in the design process. This paper proposes a novel static crosstalk noise analysis method to quickly and accurately calculate the propagation and combination of glitch noise in circuit. The key of this approach, namely transition map, is a bitmap structure which records the possible arrival times of a line. Based on it, this approach can cope with multiple coupling effects using the timing information of circuit. The analytical results for seven largest ISCAS89 benchmark circuits show that the proposed technique is highly effective in reducing the number of reported false noise violations.

关键词： Crosstalk Circuit noise Timing Noise reduction Noise figure Phase noise Information analysis Electronic equipment testing Circuit testing system testing

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Robust test generation for power supply noise induced path delay faults

Robust test generation for power supply noise induced path d...

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Asia and South Pacific Design Automation Conference

作者： Xiang Fu Huawei Li Yu Hu Xiaowei Li Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

ISBN: (纸本)9781424419210

In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS'89 circuits showed test generation can be finished in a few seconds.

关键词： Noise robustness Power generation Power supplies Noise generators Delay Circuit testing Circuit faults Timing Switches Feeds

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Data Management: The Spirit to Pursuit Peak Performance on Many-Core Processor

Data Management: The Spirit to Pursuit Peak Performance on M...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Yongbin Zhou Junchao Zhang Shuai Zhang Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

To date, most of many-core prototypes employ tiled topologies connected through on-chip networks. The throughput and latency of the on-chip networks usually become to the bottleneck to achieve peak performance especially for communication intensive applications. Most of studies are focus on on-chip networks only, such as routing algorithms or router micro-architecture, to improve the above metrics. The salient aspect of our approach is that we provide a data management framework to implement high efficient on-chip traffic based on overall many-core system. The major contributions of this paper include that: (1) providing a novel tiled many-core architecture which supports software controlled on-chip data storage and movement management; (2) identifying that the asynchronous bulk data transfer mechanism is an effective method to tolerant the latency of 2-D mesh on-chip networks. At last, we evaluate the 1-D FFT algorithm on the framework and the performance achieves 47.6 Gflops with 24.8% computation efficiency.

关键词： Network-on-a-chip Delay Prototypes Network topology Throughput Routing system-on-a-chip Communication system traffic control computer architecture Memory

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