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检索条件"机构=Key Laboratory of Computer System and Architecture "

共 402 条记录，以下是321-330 订阅

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Distributed user association for delay-load tradeoffs in energy harvesting enabled HetNets

Distributed user association for delay-load tradeoffs in ene...

引用

IEEE Wireless Communications and Networking Conference Workshops (WCNCW)

作者： Hongzhang Xu Tiankui Zhang Zhimin Zeng Dantong Liu Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing China School of Electronic Engineering and Computer Science Queen Mary University of London London UK

ISBN: (纸本)9781479987610

Energy harvesting is an emerging technology to save on-grid power and reduce carbon emissions in wireless communications. Terminals can utilize renewable energy obtained from environment by energy harvesting facilities. This paper investigates user association problem under a flow-level traffic model in energy harvesting enabled heterogeneous networks. In this paper, all the base stations are equipped with energy harvesting facilities and assumed to be solely powered by renewable energy. The average traffic delay is denoted using queuing theory, and a fairness index is redefined to evaluate the level of load balancing. Then a convex optimization problem is formulated in order to reduce average traffic delay and improve load balancing level. To this end, an iterative algorithm completed by user and base station respectively is proposed. Simulation results show that the user association algorithm improves the load balancing level with limited sacrifice on average traffic delay compared with the existing delay-optimal algorithm, and enables a flexible tradeoff between the average traffic delay and load balancing.

关键词： Load management Delays Indexes Energy harvesting Wireless communication Load modeling Renewable energy sources

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Localized random access scan: Towards low area and routing overhead

Localized random access scan: Towards low area and routing o...

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Asia and South Pacific Design Automation Conference

作者： Yu Hu Xiang Fu Xiaoxin Fan Hideo Fujiwara Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Graduate School of Information Science Nara Institute of Science and Technology Ikoma Nara Japan

ISBN: (纸本)9781424419210

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.

关键词： Routing Flip-flops Circuit testing Power dissipation Read-write memory Wires Random access memory Circuit synthesis Signal synthesis Design for testability

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A cost-effective substantial-impact-filter based method to tolerate voltage emergencies

A cost-effective substantial-impact-filter based method to t...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Songjun Pan Yu Hu Xing Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution; 2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf ) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies; 3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach.

关键词： Microprocessors Delay computer architecture Computational modeling Sensors Benchmark testing

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Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis

Observation Point Oriented Deterministic Diagnosis Pattern G...

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Asian Test Symposium (ATS)

作者： Fei Wang Yu Hu Yu Huang Jing Ye Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Mentor Graphics Corporation Marlborough MA USA

Scan is a widely used Design-for-Testability technique to improve test and diagnosis quality. Many defects may cause scan chains to fail. In this paper, an observation point oriented Deterministic Diagnostic Pattern Generation (DDPG) method was proposed for compound defects, which tolerates the system defects during scan chain diagnosis. Instead of sensitizing multiple paths proposed in our prior work, the proposed new DDPG method directly targets as many observation points as possible to observe the loading error occurred on the targeted scan cell. Experimental results on ISCASpsila89 benchmark circuits show that the proposed DDPG method improves the effectiveness and efficiency of diagnosing compound defects, compared to our prior research.

关键词： Fault diagnosis system testing Circuit faults Hardware Test pattern generators Laboratories computer architecture computer graphics Logic design Timing

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GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debugging

GVE: Godson-T Verification Engine for many-core architecture...

引用

IEEE International Conference on Field-Programmable Technology (FPT)

作者： Zhengmeng Lei Lunkai Zhang Fenglong Song Shibin Tang Dongrui Fan Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5 LX330 FPGAs, thus permitting us to map our many-core processor and peripheral devices into it. Besides the hardware, our toolkit Godson-T Studio provides the compiler, program loader, debugger and monitor to fulfil the purpose of developing, profiling and debugging, while the accuracy loss problem is settled by our novel techniques: Check-point and ILA-Check, presented in this paper. To our experience, GVE greatly reduces the verification cycle due to its high execution speed, for example, it finishes thousands of testcases in an hour, where the software-based approach takes few days to run. And by the help of the checkpoint framework, we can easily locate the faults. Because of these features, GVE makes a great contribution to the 16-tile Godson-T tape-out Project.

关键词： Clocks Field programmable gate arrays Synchronization Registers Hardware computer architecture Emulation

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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

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IEEE International Test Conference

作者： Da Wang Xiaoxin Fan Xiang Fu Hui Liu Ke Wen Rui Li Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics (Shanghai) Company Limited Shanghai China

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. ... 详细信息

关键词： Microprocessors Clocks Design for testability Circuit testing Logic testing Circuit faults Manufacturing Power dissipation CMOS technology Phase locked loops

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Trusted connection system based on virtual machine architecture

Trusted connection system based on virtual machine architect...

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International Conference on computer Science and Information Technology (CSIT)

作者： Kai Zhang Ying Song Hai-feng Fang Yu-zhong Sun Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

With the rapid development of virtualization technology, virtual machine (VM) is widely used by cloud computing - the more and more popular computing paradigm. Thus, in order to guarantee the security of cloud computing, it is necessary to securely identify the kernel of VM, the software stack running on VM and the hardware platform which VM relies on. This paper designs a system of trusted connection based on virtual machine architecture and implements a system prototype. Our system not only can securely measure and identify the kernel of VM, the software stack running on VM and the hardware platform which VM relies on, but also can realize isolations to untrusted VMs. There are three main parts in our system: trusted chain, attestation and isolation. The experiments described in this paper prove that our system ensures trusted connection of VMs and achieves isolations to untrusted VMs. The performance of our system is also analyzed and evaluated. According to the analysis results, our system is practical in terms of performance.

关键词： Variable speed drives Scalability Isolators Clouds Fires

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Graph-coloring based resource allocation scheme in relay enhanced cellular system

Graph-coloring based resource allocation scheme in relay enh...

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International Symposium on Wireless Personal Multimedia Communications (WPMC)

作者： Jinlong Cao Tiankui Zhang Zhimin Zeng Dantong Liu Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing China School of Electronic Engineering and Computer Science Queen Mary University of London London UK

ISBN: (纸本)9781479904631;9781479904631

Graph-coloring based spectrum resource allocation scheme for relay enhanced cellular (REC) system is proposed in this paper. During the signal transmission process, each subframe is split into two equal time slots (TSs). In TS1, spectrum resource allocation between base station to relay node (BS-RN) link and base station to user equipment (BS-UE) link is studied, while spectrum resources in TS2 are allocated to BS-UE link and RN-UE link. In TS1, traffic load based resource allocation scheme is applied, where the number of resources allocated to BS-RN link is according to the number of one-hop users and two-hop users. In TS2, co-channel interference is considered in the resource allocation process, which can mitigate strong interference between BS and UE, so as to achieve a higher data rate compared with conventional proportional fair (PF) resource allocation scheme. Simulation results show that the proposed scheme can obtain high average throughput as well as user fairness.

关键词： Convergence

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Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagn...

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Asian Test Symposium (ATS)

作者： Jing Ye Xiaolin Zhang Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

Volume diagnosis plays an important role in the yield learning process. To get a high quality diagnosis result, patterns with high distinguish ability are essential. However, the test patterns used by volume diagnosis commonly have low distinguish ability to specific faults. In our experiments, we observe that on average, under automatic generated test patterns, faults in the same fan out free region (FFR) account for only 6% of all possible fault pairs, but their share in total indistinguishable faults is 70%, faults in different FFRs but with the same observation points account for 4% of all fault pairs, but their share in total indistinguishable faults is 22%. Exploiting this fact that faults in the same FFRs are harder to be distinguished, we propose an Automatic Diagnostic Pattern Generation (ADPG) method named Substantial Fault Pairs at-A-Time (SFPAT)-ADPG. By applying a transformed circuit and a new fault list to an existing Automatic Test Pattern Generation (ATPG) tool, we generate the compressed test patterns which are also the diagnostic patterns with high distinguish ability for the original circuit. Experiments on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed SFPAT-ADPG method.

关键词： Circuit faults Automatic test pattern generation Benchmark testing Logic gates Transforms Integrated circuit modeling

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Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power

Design of Low-Cost High-Performance Floating-Point Fused Mul...

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International Conference on VLSI Design

作者： Zichu Qi Qi Guo Ge Zhang Xiangku Li Weiwu Hu Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

ISBN: (纸本)9781424455416

This paper presents a floating-point fused multiply-add (FMA) unit with low-cost and low power techniques. To improve the performance, two single-precision operations can be performed concurrently with one double-precision datapath, which is very useful in multimedia and even scientific applications. Moreover, to reduce the additional area costs for supporting two single-precision operations in parallel, multiple double-precision units, i.e., the multiplier, shifter and adder, are reused as much as possible. A modified dual-path algorithm is proposed by classifying the exponent difference into three cases and implementing them with close and far paths, which can reduce latency and facilitate lowering power consumption by enabling only one of the two paths. In addition, in case of FADD instructions, the multiplier in the first stage is bypassed and kept in stable mode, which can significantly improve FADD instruction performance and lower power consumption. The overall FMA unit has a latency of 4 cycles while the FADD operation has 3 cycles. Each cycle has a time delay of about 0.66 ns in the ST 65 nm CMOS technology. Compared with the conventional double-precision FMA, about 13% delay is reduced and about 22% area is increased, which is acceptable since two single-precision results can be generated simultaneously.

关键词： Costs Energy consumption CMOS technology Hardware Throughput Very large scale integration Laboratories computer architecture Delay effects Roundoff errors

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