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2008 IEEE International Symposium on Circuits and systems (ISCAS 2008), vol.10

作者： Qifei Fan Ge Zhang Weiwu Hu Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China

Dynamic voltage/frequency scaling (DVFS) has been widely applied to reduce the power dissipation of multi-cores processor. However, when applying DVFS, signals need to be synchronized between asynchronous clock domains with overhead of several cycles, which will result in performance penalty, and during frequency scaling the circuit cannot work. This paper proposes a novel variable frequency clock scheme in chip multiprocessors. In our scheme, processor cores running at different frequency can communicate with each other without the overhead of synchronizing signals. The results of simulation show that our scheme can achieve EDP improvement by 16.8percent, with only 3.6percent performance degradation.

关键词： Frequency synchronization Clocks Phase locked loops Circuits Frequency conversion Multicore processing Voltage control Degradation Dynamic voltage scaling Network-on-a-chip

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Capacity-shared heterogeneous CMP cache

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2008年第5期45卷 877-885页

作者： Gao, Xiang Zhang, Longbing Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Computer Science and Technology University of Science and Technology of China Hefei 230027 China

The characteristics of advanced integrated circuit technologies require architects to look for new ways to utilize large numbers of gates and mitigate the effects of high interconnect delays. Chip multiprocessors (CMPs) exploit increasing transistor counts by placing multiple processors on a single die. As the chip multiprocessors (CMPs) have become the trend of high performance microprocessors, the target workloads become more and more diversified. Due to the wire delay problem and diversity of applications, neither private nor shared caches can provide both large capacity and fast access in CMPs. A novel CMP cache design, the heterogeneous CMP cache (HCC) is presented, in which chips are constructed by tiles of two different categories. L2 caches of private tiles provide lowest hit latency and L2 cache of shared tiles increases the effective cache capacity for shared data. Incorporating indirect-index cache technology to share capacity between different hierarchies, HCC provide a both capacity-effective and access-fast on-chip memory subsystem. Detailed full-system simulations are used to analyze the HCC performance for various programs, including SPEC CPU2000, SPLASH2 and commercial workloads. The result shows that HCC improves performance by 16% for single-threaded benchmarks and 9% for multi-thread benchmarks. HCC is easy to implement and the design ideas will be used in the future multi-core processors of Godson series.

关键词： Microprocessor chips

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Joint LED selection and precoding optimization for multiple-user multiple-cell VLC systems

arXiv

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arXiv 2021年

作者： Yang, Yang Yang, Yujie Chen, Mingzhe Feng, Chunyan Xia, Hailun Cui, Shuguang Poor, H. Vincent The Beijing Key Laboratory of Network System Architecture and Convergence School of Information and Communication Engineering Beijing University of Posts and Telecommunications Beijing100876 China The Department of Electrical and Computer Engineering Princeton University PrincetonNJ08544 United States The Chinese University of Hong Kong Shenzhen518172 China

This paper proposes a hybrid dimming scheme based on joint LED selection and precoding design (TASP-HD) for multiple-user (MU) multiple-cell (MC) visible light communications (VLC) systems. In TASP-HD, both the LED selection and the precoding of each cell can be dynamically adjusted to reduce the intra- and inter-cell interferences while satisfying illumination constraints. First, a MU-MC-VLC system model is established, and then a sum-rate maximization problem under dimming level and illumination uniformity constraints is formulated. In this studied problem, the indices of activated LEDs and precoding matrices are optimized, which result in a complex non-convex mixed integer problem. To solve this problem, the original problem is separated into two subproblems. The first subproblem, which maximizes the sum-rate of users via optimizing the LED selection with a given precoding matrix, is a mixed integer problem solved by the penalty method. With the optimized LED selection matrix, the second subproblem which focuses on the maximization of the sum-rate via optimizing the precoding matrix is solved by the Lagrangian dual method. Finally, these two subproblems are iteratively solved to obtain a convergent solution. Simulation results verify that in a typical indoor scenario under a dimming level of 70%, the mean bandwidth efficiency of TASPHD is 4.8 bit/s/Hz and 7.13 bit/s/Hz greater than AD and DD, respectively. © 2021, CC BY-SA.

关键词： Light emitting diodes

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Data Correlation-Aware Resource Management in Wireless Virtual Reality (VR): An Echo State Transfer Learning Approach

arXiv

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arXiv 2019年

作者： Chen, Mingzhe Saad, Walid Yin, Changchuan Debbah, Mérouane Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing100876 China Wireless@VT Bradley Department of Electrical and Computer Engineering Virginia Tech BlacksburgVA United States Mathematical and Algorithmic Sciences Lab Huawei France R and D Paris

Providing seamless connectivity for wireless virtual reality (VR) users has emerged as a key challenge for future cloud-enabled cellular networks. In this paper, the problem of wireless VR resource management is investigated for a wireless VR network in which VR contents are sent by a cloud to cellular small base stations (SBSs). The SBSs will collect tracking data from the VR users, over the uplink, in order to generate the VR content and transmit it to the end-users using downlink cellular links. For this model, the data requested or transmitted by the users can exhibit correlation, since the VR users may engage in the same immersive virtual environment with different locations and orientations. As such, the proposed resource management framework can factor in such spatial data correlation, so as to better manage uplink and downlink traffic. This potential spatial data correlation can be factored into the resource allocation problem to reduce the traffic load in both uplink and downlink. In the downlink, the cloud can transmit 360 contents or specific visible contents (e.g., user field of view) that are extracted from the original 360 contents to the users according to the users' data correlation so as to reduce the backhaul traffic load. In the uplink, each SBS can associate with the users that have similar tracking information so as to reduce the tracking data size. This data correlation-Aware resource management problem is formulated as an optimization problem whose goal is to maximize the users' successful transmission probability, defined as the probability that the content transmission delay of each user satisfies an instantaneous VR delay target. To solve this problem, a machine learning algorithm that uses echo state networks (ESNs) with transfer learning is introduced. By smartly transferring information on the SBS's utility, the proposed transfer-based ESN algorithm can quickly cope with changes in the wireless networking environment due to users' conten

关键词： Virtual reality

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3-D projective moment invariants

引用

Journal of Information and Computational Science 2007年第2期4卷 821-828页

作者： Xu, Dong Li, Hua Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China Graduate University Chinese Acad. of Sci. Beijing 100080 China

2-D projective moment invariants were firstly proposed by Suk and Flusser in [12]. We point out here that there is a useless projective moment invariant which is equivalent to zero in their paper. 3-D projective moment invariants are generated theoretically by investigating the property of signed volume of a tetrahedron. The main part is the selection of permutation invariant cores for multiple integrals to generate independent and nonzero 3-D projective moment invariants. We give the conclusion that projective moment invariants don't exist strictly speaking because of their convergence problem.

关键词： computer vision

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Dependability evaluation system based on microprocessor function model

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Jisuanji Xuebao/Chinese Journal of computers 2008年第3期31卷 391-399页

作者： Zhang, Shi-Jian Xu, Tong Zhang, Long-Bing Hu, Wei-Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100039 China

With the widespread adoption of embedded microprocessor-based systems in safety critical applications, such as aircrafts, spaceships and nuclear power plants, how to rapidly and conveniently evaluate these fault-tolerant mechanisms with low cost is an important problem. The traditional method requires a detailed hardware protocol to do evaluation, which lengthens evaluation period and increases the cost. A new dependability evaluation technique based on microprocessor function model is proposed, which can evaluate fault-tolerant mechanisms more rapidly, more conveniently and more economically than the conventional systems. As a case for study, the new system evaluates three fault-tolerant techniques;the software redundancy technique, the assertion validation technique and the instruction re-fetching and re-execution technique. The results show that the evaluation is reasonable.

关键词： Fault tolerance

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Physical-annotation-based power modeling and estimation method for processor

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2007年第11期19卷 1471-1475页

作者： Huang, Kun Zhang, Ge Wang, Jun Zeng, Hongbo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The proposed method is focused on synthesis-based static circuits, and a power modeling library is developed for modeling processors by means of parametric RTL and physical annotation, and all kinds of processor modules are mapped into combinations of basic components. Those models are linked to an architectural simulator, running benchmarks to get power results. The power analysis of benchmark platforms proves to be effective and highly correlated, with an average 10% error and little speed penalty compared with the gate-level power analysis.

关键词： High performance processor Physical annotation Power estimation Power modeling

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Cache adaptive write allocate policy

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第2期44卷 348-354页

作者： Huan, Dandan Li, Zusong Hu, Weiwu Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The bandwidth becomes the major bottleneck of the performance improvement for modern microprocessors. A cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. The cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Compared with other cache store miss policies, the cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases load and store queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing the cache adaptive write allocate policy. The performance of SPEC CPU 2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.

关键词： Microprocessor chips

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Innovative architecture-level power estimation methodology for godson processor

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第5期44卷 782-789页

作者： Huang, Kun Zhang, Longbing Hu, Weiwu Zhang, Ge Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

Now the research of computer architecture focuses on how to utilize the energy of CPU to attain high performance as much as possible. Obviously the architecture-level power estimation tool is important. Existing architecture-level power simulators only focus on full-custom dynamic circuits modeling, but ignores the power modeling of ASIC designs which are mainly composed of static circuits or standard cell libraries. So this paper is concerned with the implementation of a high performance and low power general purpose CPU, the Godson-2 processor, and analyzes the power characteristics of the CPU, and implements an architecture-level power estimation methodology which aims at the Godson-2 processor. This methodology takes the power modeling methodology of CMOS static circuits into account carefully, so it is better for the estimation of current high performance CPU architecture which is designed with ASIC methodology. Compared with the RTL power estimating method, this methodology has high speed and high flexibility and the accuracy is also very good. On the platform of Intel Xeon 2.4 GHz, the speed of this methodology is about 300 K instructions per second, which is 5000 times that of the RTL power estimating method with only little error penalty.

关键词： Microprocessor chips

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Study on blocked LU decomposition on many-core architecture

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Gaojishu Tongxin/Chinese High Technology Letters 2011年第3期21卷 248-253页

作者： Yu, Lei Liu, Zhiyong Ma, Yike Song, Fenglong Xu, Weizhi Ye, Xiaochun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

The authors studied the scientific application LU decomposition deeply. A speedup model for LU decomposition was proposed, and an algorithm for LU decomposition based on bit reverse xor (BRX) was implemented. Then a dynamic absolute balance policy (DABP) algorithm was presented. In order to estimate the algorithms of 2 dimensional (2D) scatter, BRX and DABP, two different estimation functions were given and they were used to estimate the load balance problem of the algorithms. These two functions verify that the DABP algorithm has the best load balance. The simulations of the three algorithms were performed on the many-core architecture Godson-T. The experiments prove that the speedup of the DABP algorithm is 46 and it is the best performance of the three algorithms.

关键词： computer architecture

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