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检索条件"机构=Key Laboratory of Computer System and Architecture Institute of Compute Technology"
288 条 记 录,以下是101-110 订阅
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Address remapping for static NUCA in noc-based degradable chip-multiprocessors
Address remapping for static NUCA in noc-based degradable ch...
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16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010
作者: Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China
Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability ... 详细信息
来源: 评论
GVE: Godson-T verification engine for many-core architecture rapid prototyping and debugging
GVE: Godson-T verification engine for many-core architecture...
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2010 International Conference on Field-Programmable technology, FPT'10
作者: Lei, Zhengmeng Zhang, Lunkai Song, Fenglong Tang, Shibin Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing China
In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5... 详细信息
来源: 评论
Fast path selection for testing of small delay defects considering path correlations
Fast path selection for testing of small delay defects consi...
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28th IEEE VLSI Test Symposium, VTS10
作者: He, Zijian Lv, Tao Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of the Chinese Academy of Sciences Beijing China
Statistical timing models have been proposed to describe delay variations in very deep sub-micro process technologies, which have increasingly significant influence on circuit performance. Under a statistical timing m... 详细信息
来源: 评论
On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing
On Selection of Testable Paths with Specified Lengths for Fa...
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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
作者: Xiang Fu Xiaowei Li Huawei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade
Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of ... 详细信息
来源: 评论
An Efficient Algorithm for Finding a Universal Set of Testable Long Paths
An Efficient Algorithm for Finding a Universal Set of Testab...
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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
作者: Zijian He Tao Lv Xiaowei Li Huawei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academ Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academ
In this paper, we focus on generation of a universal path candidate set V that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation... 详细信息
来源: 评论
On-the-fly Reduction of Stimuli for Functional Verification
On-the-fly Reduction of Stimuli for Functional Verification
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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
作者: Qi Guo Weiwu Hu Tianshi Chen Haihua Shen Yunji Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade
As a primary method for functional verification of microprocessors, simulation-based verification has received extensive studies over the last decade. Most investigations have been dedicated to the generation of stimu... 详细信息
来源: 评论
Software-Based Self-Testing of Processors Using Expanded Instructions
Software-Based Self-Testing of Processors Using Expanded Ins...
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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
作者: Ying Zhang Xiaowei Li Huawei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade
In this paper, an automatic test instruction generation (ATIG) technique using expanded instructions is presented for software-based selftesting (SBST) of processors. First, mappings between expanded instructions and ... 详细信息
来源: 评论
Testable critical path selection considering process variation
Testable critical path selection considering process variati...
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作者: Fu, Xiang Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academic of Science Beijing 100190 China Graduate University of Chinese Academic of Sciences Beijing 100039 China
Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testabi... 详细信息
来源: 评论
Formula-Oriented Compositional Minimization in Model Checking
Formula-Oriented Compositional Minimization in Model Checkin...
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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
作者: Bowen Chen Haihua Shen Wenhui Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences Beijin
This paper presents a new approach to reduce finite state machines with respect to a CTL formula to alleviate state explosion problem. Reduction is achieved by removing parts useless to the formula of original machine... 详细信息
来源: 评论
VMGuard: An integrity monitoring system for management virtual machines
VMGuard: An integrity monitoring system for management virtu...
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16th IEEE International Conference on Parallel and Distributed systems, ICPADS 2010
作者: Fang, Haifeng Zhao, Yiqiang Zang, Hongyong Huang, H. Howie Song, Ying Sun, Yuzhong Liu, Zhiyong Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China George Washington University WA United States
A cloud computing provider can dynamically allocate virtual machines (VM) based on the needs of the customers, while maintaining the privileged access to the Management Virtual Machine that directly manages the hardwa... 详细信息
来源: 评论