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检索条件"机构=Key Laboratory of Computer System and Architecture Institute of Compute Technology"
288 条 记 录,以下是121-130 订阅
Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs  10
Accelerating Lightpath setup via broadcasting in binary-tree...
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Design, Automation and Test in Europe Conference and Exhibition
作者: Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
In this paper, we propose a binary-tree waveguide connected Optical-Network-on-Chip (ONoC) to accelerate the establishment of the lightpath. By broadcasting the control data in the proposed power-efficient binary-tree... 详细信息
来源: 评论
An abstraction-guided simulation approach using Markov models for microprocessor verification  10
An abstraction-guided simulation approach using Markov model...
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Design, Automation and Test in Europe Conference and Exhibition
作者: Tao Zhang Tao Lv Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
In order to combine the power of simulation-based and formal techniques, semi-formal methods have been widely explored. Among these methods, abstraction-guided simulation is a quite promising one. In this paper, we pr... 详细信息
来源: 评论
A general method to make multi-clock system deterministic  10
A general method to make multi-clock system deterministic
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Design, Automation and Test in Europe Conference and Exhibition
作者: Menghao Su Yunji Chen Xiang Gao Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Nondeterminism of multi-clock systems often complicates various system validation processes such as post silicon debugging and at-speed testing, which has brought many difficulties to system designers and testers. The... 详细信息
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An on-chip clock generation scheme for faster-than-at-speed delay testing  10
An on-chip clock generation scheme for faster-than-at-speed ...
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Design, Automation and Test in Europe Conference and Exhibition
作者: Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Faster-than-at-speed testing provides an effective way for detecting and debugging small delay defects in modern fabricated chips. However, the use of external automatic test equipment for faster-than-at-speed delay t... 详细信息
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Diagnosis of multiple arbitrary faults with mask and reinforcement effect  10
Diagnosis of multiple arbitrary faults with mask and reinfor...
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Design, Automation and Test in Europe Conference and Exhibition
作者: Jing Ye Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
We propose a multiple-fault diagnosis method with high diagnosability, resolution, first-hit and short run time. The method has no assumption on fault models, thus can diagnose arbitrary faults. To cope with the multi... 详细信息
来源: 评论
Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors
Address Remapping for Static NUCA in NoC-Based Degradable Ch...
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Pacific Rim International Symposium on Dependable Computing
作者: Ying Wang Lei Zhang Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability ... 详细信息
来源: 评论
nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications
nGFSIM : A GPU-based fault simulator for 1-to-n detection an...
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IEEE International Test Conference
作者: Huawei Li Dawen Xu Yinhe Han Kwang-Ting Cheng Xiaowei Li Department of Electrical and Computer Engineering University of California Santa Barbara USA Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China
We present nGFSIM, a GPU-based fault simulator for stuck-at faults which can report the fault coverage of one-to n-detection for any specified integer n using only a single run of fault simulation. nGFSIM, which explo... 详细信息
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Graph partition based path selection for testing of small delay defects  10
Graph partition based path selection for testing of small de...
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Asia and South Pacific Design Automation Conference
作者: Zijian He Tao Lv Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Critical path selection plays an important role in testing of small delay defects (SDD). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo sim... 详细信息
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High performance comparison-based sorting algorithm on many-core GPUs
High performance comparison-based sorting algorithm on many-...
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International Symposium on Parallel and Distributed Processing (IPDPS)
作者: Xiaochun Ye Dongrui Fan Wei Lin Nan Yuan Paolo Ienne Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland
Sorting is a kernel algorithm for a wide range of applications. In this paper, we present a new algorithm, GPU-Warpsort, to perform comparison-based parallel sort on Graphics Processing Units (GPUs). It mainly consist... 详细信息
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GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debugging
GVE: Godson-T Verification Engine for many-core architecture...
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IEEE International Conference on Field-Programmable technology (FPT)
作者: Zhengmeng Lei Lunkai Zhang Fenglong Song Shibin Tang Dongrui Fan Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN
In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5... 详细信息
来源: 评论