In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of acces...
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Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. ...
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Low-power design has become a challenge of test. We propose an effective low-power scan architecture named PowerSluice to minimize power consumption during scan test, which is based on scan chain modifications. On one...
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Low-power design has become a challenge of test. We propose an effective low-power scan architecture named PowerSluice to minimize power consumption during scan test, which is based on scan chain modifications. On one hand, a kind of blocking logic is inserted into the scan chain to reduce the dynamic power and two kinds of controlling units are also inserted to decrease the leakage power during the shift cycle. On the other hand, using genetic algorithm, the exact values of control signals are found out to control the process. Experiments results indicate that this architecture can effectually reduce power during scan test with probably minimum area cost.
In database systems, disk I/O performance is usually the bottleneck of the whole query processing. Among many techniques, compression is one of the most important ones to reduce disk accesses so to improve system perf...
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computerarchitectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coheren...
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In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed...
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Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time and in turn degrading the circuit perf...
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This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (Scalable Mesh of Crossbar) on-chip network and targets high-...
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The trend of using virtualization for server consolidation is more and more popular in enterprise data center. However, ondemand resource allocation among the concurrent hosted services in such a virtualized environme...
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Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much confli...
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