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Capacity-shared heterogeneous CMP cache

Jisuanji Yanjiu yu Fazhan/computer Research and Development 2008年第5期45卷 877-885页

作者： Gao, Xiang Zhang, Longbing Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Computer Science and Technology University of Science and Technology of China Hefei 230027 China

The characteristics of advanced integrated circuit technologies require architects to look for new ways to utilize large numbers of gates and mitigate the effects of high interconnect delays. Chip multiprocessors (CMPs) exploit increasing transistor counts by placing multiple processors on a single die. As the chip multiprocessors (CMPs) have become the trend of high performance microprocessors, the target workloads become more and more diversified. Due to the wire delay problem and diversity of applications, neither private nor shared caches can provide both large capacity and fast access in CMPs. A novel CMP cache design, the heterogeneous CMP cache (HCC) is presented, in which chips are constructed by tiles of two different categories. L2 caches of private tiles provide lowest hit latency and L2 cache of shared tiles increases the effective cache capacity for shared data. Incorporating indirect-index cache technology to share capacity between different hierarchies, HCC provide a both capacity-effective and access-fast on-chip memory subsystem. Detailed full-system simulations are used to analyze the HCC performance for various programs, including SPEC CPU2000, SPLASH2 and commercial workloads. The result shows that HCC improves performance by 16% for single-threaded benchmarks and 9% for multi-thread benchmarks. HCC is easy to implement and the design ideas will be used in the future multi-core processors of Godson series.

关键词： Microprocessor chips

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Testing content addressable memories using instructions and march-like algorithms

Testing content addressable memories using instructions and ...

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15th IEEE International Conference on Electronics, Circuits and systems, ICECS 2008

作者： Lin, Ma Yunji, Chen Menghao, Su Zichu, Qi Heng, Zhang Weiwu, Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704-25 Beijing 100080 China Graduate University Chinese Academy of Science Beijing 100049 China

ISBN: (纸本)9781424421824

CAM is widely used in microprocessors and SOC TLB modules. It gives great advantage for software development. And TLB operations become bottleneck of the microprocessor performance. The test cost of normal BIST approach of the CAM can not be ignored. The paper analyses the fault models of CAM and proposes an instruction suitable march-like algorithm. The algorithm requires 14N+2L operations, where N is the number of words of the CAM and L is the width of a word. The algorithm covers 100% targeted faults. Instruction-level test using the algorithm has not any test cost on area and performance. Moreover the algorithm can be used in BIST approaches and have less performance lost for microprocessors. The paper instances the algorithm in a MIPS compatible microprocessor and have good results. © 2008 IEEE.

关键词： system-on-chip

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Location Consistency Model Revisited: Problem, Solution and Prospects

Location Consistency Model Revisited: Problem, Solution and ...

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Guoping Long Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Location consistency (LC) is a weak memory consistency model which is defined entirely on partial order execution semantics of parallel programs. Compared with sequential consistency (SC), LC is scalable and provides ample theoretical parallelism. This makes LC an interesting memory model in the upcoming many-core parallel processing era. Previous work has pointed out that LC does not guarantee SC execution behavior for all data race free programs. In this paper, we compare the semantics of LC with PRAM consistency and memory coherence, and prove that LC is strictly weaker than PRAM consistency. For data race free programs, we prove that the semantics of LC is equivalent to memory coherence. In addition, by introducing memory ordering semantics into LC judiciously, we prove that the enhanced model is equivalent to SC for data race free programs. Finally, we discuss possible solutions for adding reasoning rules for LC-like weak memory models.

关键词： Coherence Phase change random access memory Distributed computing Parallel processing Programming profession Application software Laboratories Concurrent computing computer architecture Counting circuits

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An interconnect-aware power efficient cache coherence protocol for CMPs

An interconnect-aware power efficient cache coherence protoc...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Hongbo Zeng Jun Wang Ge Zhang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The continuing shrinking of technology enables more and more processor cores to reside on a single chip. However, the power consumption and delay of global wires have presented a great challenge in designing future chip multiprocessors. With these overheads of wires properly accounted for, researchers have explored some efficient on- chip network designs in the domain of larger scale caches. While in the paper, we attempt to reduce the interconnect power consumption with a novel cache coherence protocol. Conventional coherence protocols are kept independent from underlying networks for flexibility reasons. But in CMPs, processor cores and the on-chip network are tightly integrated. Exposing features of interconnect networks to protocols will unveil some optimization opportunities for power reduction. Specifically, by utilizing the location information of cores on a chip, the coherence protocol we propose in this work chooses to response the requester with the data copy in the closest sharer of the desired cache line, other than fetching it from distant L2 cache banks. This mechanism reduces the hops cache lines must travel and eliminates the power that would have incurred on the corresponding not-traveled links. To get accurate and detailed power information of interconnects, we extract wire power parameters by physical level simulation (HSPICE) and obtain router power by synthesizing RTL with actual ASIC libraries. We conduct experiments on a 16-core CMP simulator with a group of SPLASH2 benchmarks. The results demonstrate that an average of 16.3% L2 cache accesses could be optimized, resulting in an average 9.3% power reduction of data links with 19.2% as the most. This mechanism also yields a performance speedup of 1.4%.

关键词： Protocols Energy consumption Wires Network-on-a-chip Power system interconnection Delay Large-scale systems Switches Acceleration Laboratories

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Dependability evaluation system based on microprocessor function model

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Jisuanji Xuebao/Chinese Journal of computers 2008年第3期31卷 391-399页

作者： Zhang, Shi-Jian Xu, Tong Zhang, Long-Bing Hu, Wei-Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100039 China

With the widespread adoption of embedded microprocessor-based systems in safety critical applications, such as aircrafts, spaceships and nuclear power plants, how to rapidly and conveniently evaluate these fault-tolerant mechanisms with low cost is an important problem. The traditional method requires a detailed hardware protocol to do evaluation, which lengthens evaluation period and increases the cost. A new dependability evaluation technique based on microprocessor function model is proposed, which can evaluate fault-tolerant mechanisms more rapidly, more conveniently and more economically than the conventional systems. As a case for study, the new system evaluates three fault-tolerant techniques;the software redundancy technique, the assertion validation technique and the instruction re-fetching and re-execution technique. The results show that the evaluation is reasonable.

关键词： Fault tolerance

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On reducing both shift and capture power for sean-based testing

On reducing both shift and capture power for sean-based test...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Li, Jia Xu, Qiang Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture ICT Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100080 China Dept. of Computer Science and Engineering Chinese University of Hong Kong Hong Kong Center for Intelligent System and Biomimetics Institute of Advanced Integration Technology CAS/CUHK Shenzhen 518067 China

ISBN: (纸本)9781424419227

Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-filling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT's average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed methodology. ©2008 IEEE.

关键词： Filling

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Round-robin based scheduling algorithms for FIFO IQ switch

Round-robin based scheduling algorithms for FIFO IQ switch

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IEEE International Conference on Networking, Sensing and Control

作者： Xiao-jing Zhu Hong-bo Zeng Kun Huang Ge Zhang Department of Computer Science and Technology University of Science and Technology China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Network on chip (NoC) has become an active research area for high performance computer. Based on round-robin scheduling algorithm, we present three new scheduling algorithms for FIFO input queue (IQ) switches of network on chip, which are called rr-path, rr-dist and rr-al respectively, rr-path schedules the NoC traffic according to the distance between the source node and the destination node, and rr-dist schedules the NoC traffic according to the distance between the current and the destination nodes, and rr-al schedules the NoC traffic according to the difference between the arrival and the left flits numbers of every ports. We implement these algorithms in a network simulator, and analyze their performance using hotspot and uniform traffic patterns. Compared to round-robin scheduling algorithm, all of the new algorithms can reduce the max communication latency. In most cases, they can also reduce the average communication latency. Consequently, these new algorithms can improve the performance of multiprocessor systems.

关键词： Scheduling algorithm Network-on-a-chip Telecommunication traffic Traffic control Switches Round robin Processor scheduling Delay computer networks High performance computing

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Frequency method to study the propagation of transient fault in combinational logic

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2008年第5期20卷 605-611+617页

作者： Lei, Shaohua Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

This paper presents a frequency analysis method to analyze the propagation procedure of transient error in combinational logic. By using the Fourier transform with the input signal and the frequency feature of combination circuit, the output can be obtained after frequency-domain computing. A model is proposed in this paper to deal with the signals which drive the combinational logic gates working at nonlinear region. The frequency analysis method is able to provide higher accuracy, while significantly speeding up simulations. Experimental results prove that our approach is several orders of magnitude faster than HSPICE, under the guarantee of approximately 93% accuracy (compared to HSPICE).

关键词： LSI circuits

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Improving data availability for a cluster file system through replication

Improving data availability for a cluster file system throug...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Jin Xiong Jianyu Li Rongfeng Tang Yiming Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Department of Electrical & Computer Engineering and Computer Science University of Cincinnati USA

Data availability is a challenging issue for large- scale cluster file systems built upon thousands of individual storage devices. Replication is a well-known solution used to improve data availability. However, how to efficiently guarantee replicas consistency under concurrent conflict mutations remains a challenge. Moreover, how to quickly recover replica consistency from a storage server crash or storage device failure is also a tough problem. In this paper, we present a replication-based data availability mechanism designed for a large-scale cluster file system prototype named LionFS. Unlike other replicated storage systems that serialize replica updates, LionFS introduces a relaxed consistency model to enable concurrent updating all replicas for a mutation operation, greatly reducing the latency of operations. LionFS ensures replica consistency if applications use file locks to synchronize the concurrent conflict mutations. Another novelty of this mechanism is its light-weight log, which only records failed mutations and imposes no overhead on failure-free execution and low overhead when some storage devices are unavailable. Furthermore, recovery of replica consistency needs not stop the file system services and running applications. Performance evaluation shows that our solution achieves 50-70% higher write performance than serial replica updates. The logging overhead is shown to be low, and the recovery time is proportional to the amount of data written during the failure.

关键词： File systems Genetic mutations computer crashes Large-scale systems Availability Peer to peer computing Delay Bandwidth Laboratories computer architecture

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Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects

Deterministic Diagnostic Pattern Generation (DDPG) for Compo...

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IEEE International Test Conference

作者： Fei Wang Hu Yu Huawei Li Xiaowei Li Jing Ye Huang Yu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China. huyu@*** Mentor Graphics Corporation 300 Nickerson Rd. Marlborough MA 01752 USA.

Scan chain failure diagnosis has become an important means for silicon debug and yield improvement. Although plenty of prior work discussed how to perform scan chain diagnosis, most of the previously proposed techniques made an assumption that the system logic is fault-free, which could be an impractical assumption leading to incorrect diagnostic results. In this paper, we propose a scan chain deterministic diagnostic pattern generation (DDPG) method that can tolerate the faults in the system logic without degradation of chain diagnostic resolution and precision. The entire flow includes three steps. In the first step, patterns are created to propagate the state of a targeted scan cell to as many reliable observation points as possible. In the second step, the load error probability of each targeted scan cell is calculated based on the hamming distances between the observed responses and the expected good or faulty responses. In the last step, a suspect profile is plotted, which can be used to identify the suspect scan cell(s) based on ranking scores. Experimental results show that the diagnostic resolution and precision are not degraded even with dozens of faults injected into the system logic.

关键词： Fault diagnosis Degradation Hardware Logic testing Laboratories computer architecture computer graphics Silicon Error probability Logic design

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