检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

237 篇 会议
60 篇 期刊文献

馆藏范围

297 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

174 篇 工学
- 124 篇 计算机科学与技术...
- 68 篇 软件工程
- 50 篇 电子科学与技术（可...
- 21 篇 机械工程
- 18 篇 信息与通信工程
- 16 篇 控制科学与工程
- 10 篇 电气工程
- 8 篇 动力工程及工程热...
- 6 篇 材料科学与工程（可...
- 5 篇 仪器科学与技术
- 5 篇 交通运输工程
- 5 篇 生物工程
- 3 篇 光学工程
- 3 篇 冶金工程
- 3 篇 网络空间安全
- 2 篇 建筑学
- 2 篇 土木工程
- 2 篇 化学工程与技术
- 2 篇 航空宇航科学与技...
- 2 篇 环境科学与工程（可...
48 篇 理学
- 20 篇 系统科学
- 19 篇 数学
- 10 篇 物理学
- 5 篇 生物学
- 2 篇 化学
- 2 篇 统计学（可授理学、...
24 篇 管理学
- 22 篇 管理科学与工程(可...
- 7 篇 工商管理
- 4 篇 图书情报与档案管...
3 篇 经济学
- 3 篇 应用经济学
2 篇 医学
1 篇 法学
1 篇 农学

主题

57 篇 computer archite...
35 篇 laboratories
28 篇 delay
23 篇 circuit faults
22 篇 hardware
19 篇 circuit testing
18 篇 bandwidth
18 篇 costs
15 篇 protocols
15 篇 clocks
15 篇 system testing
15 篇 microprocessors
14 篇 computer network...
13 篇 fault tolerance
13 篇 automatic test p...
12 篇 switches
11 篇 system-on-a-chip
10 篇 concurrent compu...
10 篇 timing
10 篇 fault detection

机构

95 篇 key laboratory o...
83 篇 key laboratory o...
33 篇 graduate univers...
28 篇 chinese academy ...
27 篇 institute of com...
23 篇 key laboratory o...
20 篇 graduate univers...
16 篇 chinese academy ...
10 篇 graduate school ...
10 篇 chinese academy ...
10 篇 loongson technol...
9 篇 key laboratory o...
8 篇 key laboratory o...
6 篇 school of comput...
6 篇 school of comput...
5 篇 university of ch...
5 篇 graduate school ...
5 篇 state key labora...
5 篇 key laboratory o...
4 篇 key laboratory o...

作者

51 篇 xiaowei li
30 篇 huawei li
26 篇 li xiaowei
21 篇 yu hu
17 篇 yinhe han
15 篇 dongrui fan
14 篇 weiwu hu
13 篇 li huawei
13 篇 hu yu
12 篇 sun ninghui
11 篇 han yinhe
10 篇 ninghui sun
9 篇 yuzhong sun
9 篇 fan dongrui
9 篇 ying song
8 篇 hu weiwu
8 篇 zhiyong liu
8 篇 ge zhang
8 篇 liu zhiyong
8 篇 李晓维

语言

273 篇 英文
24 篇 中文

检索条件"机构=Key Laboratory of Computer System and Architecture Institute of Compute Technology"

共 297 条记录，以下是221-230 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Adaptive Diagnostic Pattern Generation for Scan Chains

Adaptive Diagnostic Pattern Generation for Scan Chains

引用

IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Fei Wang Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, a SAT-based technique is proposed to adaptively generate patterns to diagnose stuck-at faults in scan chains. Experimental results on ISCAS'89 benchmark circuits show that the proposed method can dramatically reduce the number of diagnostic patterns while obtain high diagnosis resolution.

关键词： Circuit faults Electronic equipment testing system testing Application software Circuit testing Signal resolution Failure analysis Automatic test pattern generation Frequency Test pattern generators

来源：评论

学校读者我要写书评

暂无评论

Testing content addressable memories using instructions and march-like algorithms

Testing content addressable memories using instructions and ...

引用

IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： Ma Lin Chen Yunji Su Menghao Qi Zichu Zhang Heng Hu Weiwu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

CAM is widely used in microprocessors and SOC TLB modules. It gives great advantage for software development. And TLB operations become bottleneck of the microprocessor performance. The test cost of normal BIST approach of the CAM can not be ignored. The paper analyses the fault models of CAM and proposes an instruction suitable march-like algorithm. The algorithm requires 14N+2L operations, where N is the number of words of the CAM and L is the width of a word. The algorithm covers 100% targeted faults. Instruction-level test using the algorithm has not any test cost on area and performance. Moreover the algorithm can be used in BIST approaches and have less performance lost for microprocessors. The paper instances the algorithm in a MIPS compatible microprocessor and have good results.

关键词： Associative memory computer aided manufacturing CADCAM Circuit faults Built-in self-test Circuit testing Microprocessors Costs Algorithm design and analysis Fault detection

来源：评论

学校读者我要写书评

暂无评论

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

A design- for-diagnosis technique for diagnosing both scan c...

引用

Asia and South Pacific Design Automation Conference

作者： Fei Wang Yu Hu Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424419210

The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.

关键词： Circuit faults Combinational circuits Fault diagnosis Design for disassembly Circuit testing Software testing Signal processing Flip-flops Logic Laboratories

来源：评论

学校读者我要写书评

暂无评论

MemoryIO: An Extended I/O technology in Embedded systems

MemoryIO: An Extended I/O Technology in Embedded Systems

引用

International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaojun Yang Tao Liu Fei Chen Hailiang Cheng National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Graduate University of Advanced Studies (SOKENDAI) Beijing China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyNational Research Center for Intelligent Computing Systems Chinese Academy and Sciences China

MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory system is absolutely necessary in any embedded system, and not all embedded systems integrate HyperTransport (HT), PCI Express or RapidIO interface, the MemoryIO based interconnect in embedded systems has more universalities compared with that based on HT, PCI Express or RapidIO. MemoryIO can not only thoroughly compensates for the lack of high performance data transfer channel, but also efficiently utilizes the memory bus bandwidth and the direct memory access (DMA) engine to reduce the latency for data transfer in embedded systems. This paper discusses some key technologies of MemoryIO, and presents its application in DCNet and the implementation of MemoryIO IP core. The MemoryIO technology can be used in various systems, but not limited to embedded systems.

关键词： Embedded system Payloads Switches Clocks Storage area networks Physical layer Protocols

来源：评论

学校读者我要写书评

暂无评论

A Scan-Based Delay Test Method for Reduction of Overtesting

A Scan-Based Delay Test Method for Reduction of Overtesting

引用

IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Hui Liu Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper presents a scan-based delay test method, called sequential-broad-side (SeBoS), to minimize overtesting of delay test. We consider two critical reasons for overtesting which are the existence of illegal states in sequential circuits and the high IR drop caused by power dissipation during structural test. The proposed SeBoS method inserts several slow clock cycles before applying the fast clock for detecting delay faults, thus considerable illegal states can be avoided and IR drop can be reduced. Illegal states are not necessarily computed before test generation. They can be accumulated and expanded during the automatic test pattern generation (ATPG) process. The derived illegal states are then used to guide test generation for the remaining faults. Compared with previous methods, the SeBoS method can avoid more illegal states when considering the same number of time frames. Experimental results on ISCAS-89 benchmark circuits show the effectiveness of the method.

关键词： Delay Circuit testing Sequential analysis Clocks Circuit faults Automatic test pattern generation Sequential circuits Power dissipation Electrical fault detection Fault detection

来源：评论

学校读者我要写书评

暂无评论

A Network Memory architecture Model and Performance Analysis

A Network Memory Architecture Model and Performance Analysis

引用

International Conference on Networking, architecture, and Storage (NAS)

作者： Li Liu Mingyu Chen Yungang Bao Jianwei Xu Jianping Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

This paper presents a network memory architecture and makes a performance model to analysis the slowdown caused by the remote access delay. In this architecture the network memory is accessed through a smart network memory controller. A local page cache and a virtual page prefetching engine are designed in the smart network memory controller to improve the memory access performance.

关键词： Prefetching Delay Memory architecture Memory management computer architecture Engines Monitoring

来源：评论

学校读者我要写书评

暂无评论

Static Crosstalk Noise Analysis with Transition Map

Static Crosstalk Noise Analysis with Transition Map

引用

IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Minjin Zhang Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

As the feature size scales into the nanometer era, crosstalk noise begins to exert a more significant adverse influence on circuit and need to be estimated efficiently in the design process. This paper proposes a novel static crosstalk noise analysis method to quickly and accurately calculate the propagation and combination of glitch noise in circuit. The key of this approach, namely transition map, is a bitmap structure which records the possible arrival times of a line. Based on it, this approach can cope with multiple coupling effects using the timing information of circuit. The analytical results for seven largest ISCAS89 benchmark circuits show that the proposed technique is highly effective in reducing the number of reported false noise violations.

关键词： Crosstalk Circuit noise Timing Noise reduction Noise figure Phase noise Information analysis Electronic equipment testing Circuit testing system testing

来源：评论

学校读者我要写书评

暂无评论

Robust test generation for power supply noise induced path delay faults

Robust test generation for power supply noise induced path d...

引用

Asia and South Pacific Design Automation Conference

作者： Xiang Fu Huawei Li Yu Hu Xiaowei Li Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

ISBN: (纸本)9781424419210

In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS'89 circuits showed test generation can be finished in a few seconds.

关键词： Noise robustness Power generation Power supplies Noise generators Delay Circuit testing Circuit faults Timing Switches Feeds

来源：评论

学校读者我要写书评

暂无评论

Localized random access scan: Towards low area and routing overhead

Localized random access scan: Towards low area and routing o...

引用

Asia and South Pacific Design Automation Conference

作者： Yu Hu Xiang Fu Xiaoxin Fan Hideo Fujiwara Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Graduate School of Information Science Nara Institute of Science and Technology Ikoma Nara Japan

ISBN: (纸本)9781424419210

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.

关键词： Routing Flip-flops Circuit testing Power dissipation Read-write memory Wires Random access memory Circuit synthesis Signal synthesis Design for testability

来源：评论

学校读者我要写书评

暂无评论

Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor

Fetching Primary and Redundant Instructions in Turn for a Fa...

引用

Pacific Rim International Symposium on Dependable Computing

作者： Shijian Zhang Weiwu Hu Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

With the development of semiconductor technology, microprocessors become more and more susceptible to transient faults. Some proposed schemes support redundant execution of a program in a superscalar processor for fault tolerance. However, they require a huge queue to accommodate interim states, which enlarge the hardware cost significantly. This paper analyzes the effect of halving a processor¿s instruction fetch bandwidth on a program¿s performance. We find that the performance degradation resulted from halving instruction fetch bandwidth declines when instruction latency is lengthened, branch prediction accuracy deteriorates or cache miss rate increases. Since an embedded microprocessor is characterized by long instruction latency, high branch misprediction rate and cache miss rate, a fault-tolerant scheme is proposed, in which two threads fetch instructions in turn and execute in the same processor core simultaneously without any extra queue. The simulation results from eight embedded applications show that performance penalty of our solution ranges from 6.5% to 30.1%, with an average of 22.5%, which is lower than that of the other proposed schemes. The experiment also indicates that our scheme can effectively detect faults occurring in the entire pipeline with short fault detection latency and minimal hardware cost. It is well suited for our solution to realize a reliable embedded microprocessor.

关键词： Fault tolerance Microprocessors Delay Hardware Costs Bandwidth Fault detection Performance analysis Degradation Accuracy

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共30页 << < 19 20 21 22 23 24 25 26 27 28 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：