检索结果-内蒙古大学图书馆

15th IEEE International Conference on Electronics, Circuits and systems, ICECS 2008

作者： Lin, Ma. Yan, Gao Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704-25 Beijing 100190 China College of Electronics and Information Engineering Tongji University SiPing Road 1239 Shanghai 200092 China Graduate University of Chinese Academy of Science Beijing 100049 China

ISBN: (纸本)9781424421824

Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test results. But for the multipliers, one important part of microprocessors, there is no detail on how to testing them. This paper presents an instruction level test approach for the multiplier test. The proposed approach does not modify the multipliers and does not need any extra logic just using instructions of the processors to test processors' multipliers. Sequentially it does not have any test cost on area or timing. Moreover the instruction-level test is suited for at-speed test in nature. Experimental results on the real processor's circuits show that the instruction level test approach has good effect on parallel multipliers © 2008 IEEE.

关键词： system-on-chip

来源：评论

学校读者我要写书评

暂无评论

A Case Study on At-Speed Testing for a Gigahertz Microprocessor

A Case Study on At-Speed Testing for a Gigahertz Microproces...

引用

IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Da Wang Rui Li Yu Hu Huawei Li Xiaowei Li Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics Company Limited Shanghai China

This paper describes a low cost, high quality at-speed testing strategy implemented on a gigahertz microprocessor with multi-clock domains. The presented DFT method not only utilizes the internal phase-locked loops (PLLs) to provide complex test clock sequences, but also applies a hybrid scan compression structure to reduce test data volume. It is difficult and time-consuming to generate at-speed tests for a design with embedded memories and multi-clock domains. The proposed test pattern generation scheme can gain transition fault coverage of approximately 83% for this high-performance microprocessor, and the test power consumption is well controlled.

关键词： Microprocessors Circuit testing Clocks Logic testing system testing Electronic equipment testing Test pattern generators Costs Circuit faults Energy consumption

来源：评论

学校读者我要写书评

暂无评论

A HyperTransport-based personal parallel computer

A HyperTransport-based personal parallel computer

引用

IEEE International Conference on Cluster Computing

作者： Xiaojun Yang Fei Chen Hailiang Cheng Ninghui Sun Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Instead of all using commodity components, an approach building a personal parallel computer on top of a non-coherent HyperTransport (HT) fabric is presented in the paper. The advantage is to provide both lower cost and higher performance compared with the existing method. A HT switch is designed and implemented for the interconnection of a set of AMD Opteron processors for building an in-a-box cluster. On our prototyping system, the result of evaluation experiments shows this approach gives the better performance.

关键词： Switches Program processors computers Bandwidth Fabrics Protocols computer architecture

来源：评论

学校读者我要写书评

暂无评论

A novel hint-based I/O mechanism for centralized file server of cluster

A novel hint-based I/O mechanism for centralized file server...

引用

IEEE International Conference on Cluster Computing

作者： Huan Chen Jin Xiong Ninghui Sun Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy and Sciences Beijing China Key Laboratory of Computer Architecture and System Chinese Academy and Sciences Beijing China

In the medium and small cluster systems, the centralized file server such as NFS is the main approach to provide the storage service with low cost and easy management. However, when multiple parallel applications access the shared storage at the same time, the I/O performance decreases much because of the interference of the I/O requests coming from the different clients. In this paper, a hint-based I/O mechanism is proposed and implemented in the United-FS. By analyzing the hint information of the I/O requests, the related requests are grouped, sorted and scheduled by our hint-based I/O scheduler. The experiments show that our hint-based I/O mechanism nearly doubles the read performance compared with NFS, and has better scalability.

关键词： File systems Servers File servers Performance evaluation Bandwidth Scalability Time factors

来源：评论

学校读者我要写书评

暂无评论

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis

Observation Point Oriented Deterministic Diagnosis Pattern G...

引用

Asian Test Symposium (ATS)

作者： Fei Wang Yu Hu Yu Huang Jing Ye Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Mentor Graphics Corporation Marlborough MA USA

Scan is a widely used Design-for-Testability technique to improve test and diagnosis quality. Many defects may cause scan chains to fail. In this paper, an observation point oriented Deterministic Diagnostic Pattern Generation (DDPG) method was proposed for compound defects, which tolerates the system defects during scan chain diagnosis. Instead of sensitizing multiple paths proposed in our prior work, the proposed new DDPG method directly targets as many observation points as possible to observe the loading error occurred on the targeted scan cell. Experimental results on ISCASpsila89 benchmark circuits show that the proposed DDPG method improves the effectiveness and efficiency of diagnosing compound defects, compared to our prior research.

关键词： Fault diagnosis system testing Circuit faults Hardware Test pattern generators Laboratories computer architecture computer graphics Logic design Timing

来源：评论

学校读者我要写书评

暂无评论

A service-oriented priority-based resource scheduling scheme for virtualized utility computing 08

引用

Proceedings of the 15th international conference on High performance computing

作者： Ying Song Yaqiong Li Hui Wang Yufang Zhang Binquan Feng Hongyong Zang Yuzhong Sun Key Lab. of Computer System and Architecture Inst. of Computing Techn. Chinese Academy of Sciences China and National Research Center for Intelligent Computing Systems ICT China and Graduate Univ. of Chinese Academy of Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China and National Research Center for Intelligent Computing Systems ICT China

ISBN: (纸本)9783540898931

In order to provide high resource utilization and QoS assurance inutility computing hosting concurrently various services, this paper proposes aservice computing framework-RAINBOW for VM(Virtual Machine)-basedutility computing. In RAINBOW, we present a priority-based resourcescheduling scheme including resource flowing algorithms (RFaVM) to optimizeresource allocations amongst services. The principle of RFaVM is preferentiallyensuring performance of some critical services by degrading of others to someextent when resource competition arises. Based on our prototype, we evaluateRAINBOW and RFaVM. The experimental results show that RAINBOWwithout RFaVM provides 28%-324% improvements in service performance,and 26% higher the average CPU utilization than traditional service computingframework (TSF) in typical enterprise environment. RAINBOW with RFaVMfurther improves performance by 25%-42% for those critical services whileonly introducing up to 7% performance degradation to others, with 2%-8%more improvements in resource utilization than RAINBOW without RFaVM.

关键词： resource scheduling utility computing virtualization

来源：评论

学校读者我要写书评

暂无评论

Multiple Coupling Effects Oriented Path Delay Test Generation

Multiple Coupling Effects Oriented Path Delay Test Generatio...

引用

26th IEEE VLSI Test Symposium (VTS 2008)

作者： Minjin Zhang Huawei Li Xiaowei Li Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Academy of Sciences Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

We propose a two-phase test generation method to generate patterns targeting maximal path delay caused by multiple crosstalk effects. A timing analysis method based on transition map is proposed to manage the timing information of aggressor lines and victim lines in the first phase, followed by an ordinary ATPG engine with a few alterations in the second phase. This two-phase method avoids complex timing processing in ATPG algorithm. Using transition map instead of timing window in timing analysis, our method can more efficiently calculate the accumulative crosstalk-induced delay and find the sub-paths which cause maximal coupling effects. We can trade off accuracy and efficiency by controlling the size of timescale used in transition map, which makes this approach highly scalable.

关键词： Delay effects Testing Timing Test pattern generators Crosstalk Automatic test pattern generation Information analysis Information management Engines Cause effect analysis

来源：评论

学校读者我要写书评

暂无评论

Deterministic Circular Self Test Path

引用

Tsinghua Science and technology 2007年第S1期12卷 20-25页

作者：文科胡瑜李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental re- sults on ISCAS’89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

关键词： very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic

来源：评论

学校读者我要写书评

暂无评论

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects

Codeword Selection for Crosstalk Avoidance and Error Correct...

引用

26th IEEE VLSI Test Symposium (VTS 2008)

作者： Ying Zhang Huawei Li Xiaowei Li Yu Hu Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Crosstalk effects and soft errors on interconnects have been increasingly serious, which affects normal communication among cores. Therefore, it is desirable to design a reliable bus system without causing unacceptable performance reduction. In this paper, a new bus encoding method based on codeword selection is presented for enduring crosstalk-induced effects, which can avoid crosstalk and provide error correction as well. This method finds a subset from crosstalk avoidance code (CAC) to provide error correction. It can avoid crosstalk induced by late signal transition on checking bits in the previous methods. Extra wires for checking bus are never required in the proposed method. Experiment shows that the method reduces 6% wire overhead compared to the former methods. And it can also improve bus performance and reduce power dissipation.

关键词： Crosstalk Error correction codes Wires Delay Encoding Very large scale integration Power system interconnection Digital audio players Error correction Capacitance

来源：评论

学校读者我要写书评

暂无评论

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

引用

Journal of computer Science & technology 2007年第5期22卷 673-680页

作者：王伟胡瑜韩银和李晓维张佑生 School of Computer and Information Hefei University of Technology Hefei 230009China Key Laboratory of Computer System and ArchitectureInstitute of Computing TechnologyChinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080China School of Computer and Information Hefei University of Technology Hefei 230009China

It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,

关键词： leakage current don＇t care bits minimum leakage vector leakage power

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：