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2007 1st International Conference on Bioinformatics and Biomedical Engineering, ICBBE

作者： Ma, Zhaoyun Zhang, Fa Xu, Lin Feng, Shengzhong Liu, Zhiyong Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Graduate School Chinese Academy of Sciences

ISBN: (纸本)1424411203

Homology modeling, as a successful protein structure prediction method, has two major deficiencies, i.e., the lack of the templates (known structures), and the accuracy of alignment between the query (unknown structure) and its templates. To solve these problems, we have constructed a conservative domain clustering template database, and proposed a profile-based alignment algorithm based on the profile extracted from each domain clustering in the database. The extracted profile can well represent the information of the sequence and structure as well. Compared with other alignment methods, such as T-coffee and Smith-Water man, our results show that with this method it's possible to obtain a higher hit rate for template searching and a more accurate and reliable query-template alignment. Therefore, the quality of protein structure prediction can be improved. © 2007 Crown Copyright.

关键词： Proteins

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Regular Paper: A Study of Architectural Optimization Methods in Bioinformatics Applications

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The International Journal of High Performance Computing Applications 2007年第3期21卷 371 - 384页

作者： G. Tan L. Xu Z. Dai S. Feng N. Sun KEY LABORATORY OF COMPUTER SYSTEM AND ARCHITECTURE INSTITUTE OF COMPUTING TECHNOLOGY CHINESE ACADEMY OF SCIENCES BEIJING CHINA KEY LABORATORY OF COMPUTER SYSTEM AND ARCHITECTURE INSTITUTE OF COMPUTING TECHNOLOGY CHINESE ACADEMY OF SCIENCES BEIJING CHINA

Studies in the optimization of sequence alignment have been carried out in bioinformatics. In this paper, we have focused on two aspects: memory usage and execution time. Our study suggests that cache memory does not have a significant effect on system performance. Our attention then turns to optimize Smith—Waterman's algorithm. Two instruction level methods have been proposed and 2—8 fold speed improvements have been observed after the optimization has been implemented. Further improvements on system performance have been achieved by overlapping computation with system I/O usage.

关键词： bioinformatics sequence alignment cache memory instruction level parallelism I/O overlapping

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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

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2007 IEEE International Test Conference, ITC

作者： Wang, Da Fan, Xiaoxin Fu, Xiang Liu, Hui Wen, Ke Li, Rui Li, Huawei Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Beijing China Co. Ltd. Shanghai China

ISBN: (纸本)1424411289

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals. © 2007 IEEE.

关键词： Design for testability

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Deterministic Circular Self Test Path

Deterministic Circular Self Test Path

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第十二届全国容错计算学术会议

作者： WEN Ke HU Yu LI Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100％ fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

关键词： very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic

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Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects

Test Generation for Crosstalk Glitches Considering Multiple ...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Minjin Zhang Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

As the feature size continues to scale into the nanometer era, crosstalk-induced effect begins to exert a more significant influence. In this paper, we address the condition of maximum crosstalk glitch noise considering multiple coupling effects and propose a novel test generation technique for this problem. A multiple crosstalk-induced glitch fault (MCGF) model is introduced, which gives information on one or more sub-paths to be sensitized to generate transitions coupled to a victim line. The test for an MCGF is a 2-vector pattern that sensitizes the transition signal along the sub-path to each aggressor line at the maximum aggressive time (MAT), and propagates the signal on a victim line to an output. A new structure, transition map (TM), is proposed to record all the possible arrival time of a line. The MAT of a victim line is calculated based on effective coupling capacitance (ECC). Therefore, the crosstalk-induced effects can be effectively identified, and exactly activated using the generated test patterns. Experiments on ISCAS89 benchmark circuit show that the proposed technique can be applied to circuits of reasonable sizes within acceptable time.

关键词： Crosstalk Circuit faults Timing Test pattern generators system testing Noise generators Coupling circuits Capacitance Circuit noise Automatic test pattern generation

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Fault Tolerance Mechanism in Chip Many-Core Processors

Fault Tolerance Mechanism in Chip Many-Core Processors

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第十二届全国容错计算学术会议

作者： ZHANG Lei HAN Yinhe LI Huawei LI Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors'yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors'performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8％ degradation with negligible computing time.

关键词： chip many-core processors yield fault tolerance reconfiguration network-on-chip

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Online Distributed Fault Detection of Sensor Measurements

Online Distributed Fault Detection of Sensor Measurements

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第十二届全国容错计算学术会议

作者： GAO Jianliang XU Yongjun LI Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may make inappropriate decisions when it receives the incorrect data sent by the faulty sensors. To solve these problems, this paper develops an online distributed algorithm to detect such faults by exploring the weighted majority vote scheme. Considering the spatial correlations in WSNs, a faulty sensor can diagnose itself through utilizing the spatial and time information provided by its neighbor sensors. Simulation results show that even when as many as 30％ of the sensors are faulty, over 95％ of faults can be correctly detected with our algorithm. These results indicate that the proposed algorithm has excellent performance in detecting fault of sensor measurements in WSNs.

关键词： wireless sensor networks fault diagnosis fault detection fault tolerance spatial correlation

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Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic

Frequency Analysis Method for Propagation of Transient Error...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Shaohua Lei Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

The continuous development of VLSI technology is shrinking the minimal sizes to nanometer region, making circuits more susceptible to transient error. In this paper, we present a frequency analysis method to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We use the frequency feature of signal and frequency response of electrical system to analyze the propagation of transient error. Experiments show that on average, our approach provides approximately 95％ accuracy and several orders of magnitude faster with respect to HSPICE simulation.

关键词： Transient analysis Frequency estimation CMOS logic circuits Very large scale integration CMOS technology Circuit faults Combinational circuits Frequency response Signal analysis Circuit simulation

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CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors

CREA: A Checkpoint Based Reliable Micro-architecture for Sup...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Shijian Zhang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

Conventional temporal redundant techniques to detect transient faults have resulted in considerable performance loss. One major reason for this problem is the reclamation of some critical resources, such as the instruction window and physical registers, is delayed, which degrades instruction-level parallelism. This paper proposes a novel fault- tolerant micro-architecture based on checkpoint mechanism. All occupied resources are reclaimed during the retirement stage in the first execution. Therefore, the performance overhead is mitigated evidently. Our scheme requires only small hardware cost and provides short fault detection latency.

关键词： Registers Fault detection Retirement Hardware Costs Delay Pipelines Buffer storage Redundancy Yarn

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A routing algorithm for random error tolerance in network-on-chip

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12th International Conference on Human-computer Interaction, HCI International 2007

作者： Zhang, Lei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences 100080 Beijing China Graduate University Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9783540731092

In DSM and nanometer technology, there will present more and more new fault types, which are difficult to predict and avoid. Applying fault tolerant algorithms to achieve reliable on-chip communication is one of the most important issues of Network-on-Chip (NoC). This paper reviews the main on-chip fault tolerant communication algorithms and then proposes a new routing algorithm with end-to-end feedback. The average transmission latency, power consumption and reliability are compared with other techniques. As experiments show, the proposed algorithm has lower latency, lower power consumption compared with those of others, and it can provide high reliability. © Springer-Verlag Berlin Heidelberg 2007.

关键词： Routing algorithms

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