This paper proposed hierarchical fault tolerance techniques for ultrahigh-density memories based on 3- dimension interconnect technology. It describes how to implement hierarchical architecture with different granular...
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This paper proposed hierarchical fault tolerance techniques for ultrahigh-density memories based on 3- dimension interconnect technology. It describes how to implement hierarchical architecture with different granularity redundancies and how to combine error correction code (ECC), built-in self-test (BIST), built-in repair-analysis (BIRA), and built-in self-repair (BISR) capabilities. Simulation is employed to estimate the memory behavior of various configurations, and experimental results indicate that the proposed method has substantial reliability improvements over conventional techniques. For a memory with 1% bit-level failure rate and 50% device-level defect density, the proposed method can gain 100% reliability by using less than 30% extra overhead. It proves the availability of the proposed architecture.
Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for sil...
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Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.
An effective interconnect network interface card (NIC) is critical to the achievement of a high-performance cluster system. An original NIC architecture based on the Intel IOP310 I/O processor chipset is presented in ...
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An effective interconnect network interface card (NIC) is critical to the achievement of a high-performance cluster system. An original NIC architecture based on the Intel IOP310 I/O processor chipset is presented in this paper. The NIC is a part of DCNet, which is the cluster interconnect network developed by NCIC. The I/O processor makes it powerful for the NIC to offload the processing of communication protocol from the host CPU. In the NIC architecture, the memory bus is extended to be a local bus for system peripheral interconnection, and a memory integrated network interface (MINI) is implemented and embedded. The testing results of DCNet show that the NIC obtains reasonable user-level communication performance, and prove that the NIC architecture, which based on I/O processor and the MINI approach, is feasible and effective to achieve the high performance.
This paper presents the item-missing error model. It stems from the analysis of real bugs that are collected in two market-oriented projects: (1) the AMBA interface of a general-purpose microprocessor IP core; (2) a w...
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This paper presents the item-missing error model. It stems from the analysis of real bugs that are collected in two market-oriented projects: (1) the AMBA interface of a general-purpose microprocessor IP core; (2) a wireless sensor network oriented embedded processor. The bugs are analyzed via code structure comparison, and it is found that item-missing errors merit attention. The test generation method for item-missing error model is proposed. Structural information obtained from this error model is helpful to reach a greater probability of bug detection than that in random-generation verification with only functional constraints. Finally, the proposed test method is applied in verification of our designs, and experimental results demonstrate the effectiveness of this method.
In this paper,volume models are obtained from closed surface models by an accurate voxelization method which can handle the hidden cavities. This kind of 3D binary images is then converted to gray-level images by a fa...
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In this paper,volume models are obtained from closed surface models by an accurate voxelization method which can handle the hidden cavities. This kind of 3D binary images is then converted to gray-level images by a fast Euclidean distance transform (EDT).Moment invariants (MIs) which are invariant shape descriptors under similarity transformations,are then computed based on the gray images. Applications in shape analysis area such as principal axis determination,skeleton and medial axis extraction,and shape retrieval can be carried out base on EDT and MIs.
Low-power design is one of the most important issues in wireless sensor networks (WSNs), while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make th...
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Low-power design is one of the most important issues in wireless sensor networks (WSNs), while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make the power consumption down, but excessive interferences from potential adjacent operating links and communication reliability between nodes should be considered. In this paper, a reliable and energy efficient protocol is presented, which adopts adaptive rate control based on an optimal TP. A mathematical model considering average interference and network connectivity was used to predict the optimal TP. Then for the optimal TP, active nodes adaptively chose the data rate with the change of bit-error-rate(BER) performance. The efficiency of the new strategy was validated by mathematical analysis and simulations. Compared with 802.11 DCF which uses maximum unified TP and BASIC protocol, it is shown that the higher average throughput can achieve while the energy consumption per useful bit can be reduced according to the results.
This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. ...
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This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals.
It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to sim...
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It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors (CMPs). Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced.
Dynamic programming has been one of the most efficient approaches to sequence analysis and structure prediction in biology. However, their performance is limited due to the drastic increase in both the number of biolo...
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Ubiquitous sensor networks are application oriented system, which are composed of a large number of cooperative sensor nodes. The identification of individual sensor node is important especially for some security-sens...
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Ubiquitous sensor networks are application oriented system, which are composed of a large number of cooperative sensor nodes. The identification of individual sensor node is important especially for some security-sensitive applications. In this paper, we focus on the establishment of trust relationship among wireless sensor nodes, and try to combine the message authentication and identity authentication as a countermeasure to hostile attack. Accompanied with a simple lightweight key pre-distribution algorithm, in which each node sends only one message, we propose a lightweight trust relationship establishing scheme for ubiquitous sensor networks. The new scheme, which works without a trusted authority in the network, is not only concise in format but effective in practice to ensure network trusted and secure.
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