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2007 IEEE International Symposium on Circuits and systems, ISCAS 2007

作者： Jun, Wang Ge, Zhang Weiwu, Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100080 China

As the gap between processing capability and bandwidth requirement of microprocessor increases, optical interconnects are used more and more widely in chip-to-chip data links. Trade-offs are made among latency, area, power consumption and reliability in the high frequency interconnect system in which error control schemes are always implemented to make it tolerate PER (packet error rate). In this paper, a scalable system for chip-to-chip optical interconnects is proposed and different types of error control schemes are compared using 90nm CMOS process. The goals are set to low latency, small area and low power consumption as well as acceptable MTTF (mean time to failure) for USR (ultra-short-reach) with very low BER (bit error rate). After that the ECS-HC based system is picked out and validated based on FPGA and 4.25Gbps 850nm optical transceivers. © 2007 IEEE.

关键词： Error correction

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Computation pattern driven reuse of manual optimizations for GPGPUs

Computation pattern driven reuse of manual optimizations for...

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2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2011

作者： Xu, Shixiong Han, Dongni Chen, Li Key Laboratory of Computer System and Architecture Institute of Computing Technology University of Chinese Beijing China

ISBN: (纸本)9780769545646

The wide application of General Purpose Graphic Processing Units (GPGPUs) results in large manual efforts on porting and optimizing algorithms on them. However, most existing automatic ways of generating GPGPU code fail to conduct optimization strategies regarding a specific computation and to reuse constantly evolving manual optimizations. In this paper, we present a computation pattern driven approach for computation-specific GPGPU code generation and optimization, which in turn reuses manual optimizations to a certain extent. We suggest language extensions to OpenMP, high-level data structure attributes, in order to assist the process of computation pattern matching and to help give users intuitive performance tuning parameters in the view of data structure attributes. We illustrate the feasibility of this approach through three important computation dwarfs, which are dense matrix, sparse matrix, and structured mesh computation in scientific computing. We also build a prototype OpenMP-to-CUDA translator that consists of computation pattern recognition and code template instantiation. The experimental results demonstrate the performance benefits of computation pattern driven method. To our best knowledge, it is the first work on reusing manual optimizations for GPGPUs with computation pattern driven approach. © 2011 IEEE.

关键词： Data structures

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An energy-efficient scheduling approach based on private clouds

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Journal of Information and Computational Science 2011年第4期8卷 716-724页

作者： Li, Jiandun Peng, Junjie Lei, Zhou Zhang, Wu School of Computer Engineering and Science Shanghai University Shanghai 200072 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing 100190 China

With further development and wide acceptance of cloud computing, lots of companies and colleges decide to take advantage of it in their own data centers, which is known as private clouds. Since private clouds have some unique characteristics and special requirements, it is still a challenging problem to effectively schedule virtual machine requests onto compute nodes, especially with multiple objectives to meet. In this paper, we explore couples of characteristics related to workflow scheduling in the scenario of private clouds and propose a hybrid energy-efficient scheduling approach. The experiments show that it can save more time for users, conserve more energy and achieve higher level of load balancing. Copyright © 2011 Binary Information Press.

关键词： Cloud computing

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A Dependability Model for TMR system

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International Journal of Automation and computing 2012年第3期9卷 315-324页

作者： Peng, Jun-Jie Liu, Yan-Ping Chen, Yuan-Yuan School of Computer Engineering and Science Shanghai University Shanghai 200072 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Much research has been done on the dependability evaluation of computer systems. However, much of this is gone no further than study of the fault coverage of such systems, with little focus on the relationship between fault coverage and overall system dependability. In this paper, a Markovian dependability model for triple-modular-redundancy (TMR) system is presented. Having fully considered the effects of fault coverage, working time, and constant failure rate of single module on the dependability of the target TMR system, the model is built based on the stepwise degradation strategy. Through the model, the relationship between the fault coverage and the dependability of the system is determined. What is more, the dependability of the system can be dynamically and precisely predicted at any given time with the fault coverage set. This will be of much benefit for the dependability evaluation and improvement, and be helpful for the system design and maintenance.

关键词： Dependability Markovian model coverage triple-modular-redundancy (TMR) failure rate.

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Using index in the MapReduce framework

Using index in the MapReduce framework

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12th International Asia Pacific Web Conference, APWeb 2010

作者： An, Mingyuan Wang, Yang Wang, Weiping Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Beijing China

ISBN: (纸本)9780769540122

MapReduce is a programming framework introduced by Google for large-scale data processing. It is usually used in a scan-centric fashion where all the data are split into blocks and Maps are generated for each block to scan and process the data in the block, then Reduces merge outputs from all the Maps. When a query intends to process only a subset of the data selected by a predicate, this brute-force method may cause extra I/O overhead spent on irrelevant data, and the overhead for initiating so many Maps may be nontrivial given that the actually interesting data for the query is comparatively small in volume. We propose an approach to integrate the index into the MapReduce execution in which only an appropriate number of Maps are generated, each of which accesses the data using an index. This approach incurs random I/O and remote access to data, so the overall performance depends on both system parameters and the query characteristics. We build a cost model for both this index access execution and the traditional full scan execution. This cost model can be used to choose between the two execution modes before executing a query. Experiments show that the index access execution can greatly outperform full scan execution when the selectivity of the predicate is low, and the cost model predicts the actual execution cost very well so can be used to determine the execution plan for a query. © 2010 IEEE.

关键词： MapReduce

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A parallel algorithm for computing betweenness centrality

A parallel algorithm for computing betweenness centrality

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38th International Conference on Parallel Processing, ICPP-2009

作者： Tan, Guangming Tu, Dengbiao Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769538020

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n + m) space and O(nm/p ) ( or O(nm+n2logn /p )) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times. © 2009 IEEE.

关键词： Parallel algorithms

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Software and hardware cooperate for 1-D FFT algorithm optimization on multicore processors

Software and hardware cooperate for 1-D FFT algorithm optimi...

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IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Zhou, Yongbin Zhang, Junchao Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier Transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency. © 2009 IEEE.

关键词： Fast Fourier transforms

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Circuit implementation of floating point range reduction for trigonometric functions

Circuit implementation of floating point range reduction for...

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2007 IEEE International Symposium on Circuits and systems, ISCAS 2007

作者： Xuehai, Qian Hao, Zhang Jingang, Yang He, Huang Junchao, Zhang Dongrui, Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Range reduction is important in evaluating trigonometric functions but not enough work is done in relation to the hardware implementation of it. A hardware floating point range reduction implementation is presented. The whole reduction is divided into two steps;the first is based on Double-Residue modular range reduction method and the second adopts on a novel method described in this paper. The latter one can reduce the argument to an arbitrary range and provides the number of times that range constant contained in the argument It has been synthesized using 0.13 um library to achieve an approximately 700 MHz operation frequency. © 2007 IEEE.

关键词： Digital circuits

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Snooping and ordering ring - An efficient cache coherence protocol for ring connected CMP

Snooping and ordering ring - An efficient cache coherence pr...

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15th International Conference on Parallel and Distributed systems, ICPADS '09

作者： Cao, Fei Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769539003

Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. Existing ring protocols, such as the snooping ring protocol and the ring-order protocol need a retry and acknowledgement scheme or use the ordering property of the ring respectively to resolve conflict memory requests. A cache coherence protocol named SOR (Snooping and Ordering Ring) is developed for ring connected CMP in this paper. This protocol is based on the snooping ring protocol. But instead of using the acknowledgement and retry scheme, it uses the ordering property of the ring to resolve conflicts, thus can avoid unnecessary retries to improve performance and power efficiency. The L1 snooping results are sent with the requests instead of being delayed, so that many useless snoops can be avoided. Simulation result shows that the average probe slot transports and snoop operations can be reduced by SOR are 47% and 48.9%. The average and maximum performance improvements by SOR are 3.33% and 6%. © 2009 IEEE.

关键词： Packet switching

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Co-optimization of Dynamic/Static Test PoWer in Scan Test

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电子学报(英文版) 2009年第1期18卷 54-58页

作者： WANG Wei HAN Yinhe LI Xiaowei FANG Fang School of Computer and Information Hefei University of Technology Hefei 230009 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China School of Management Hefei University of Technology Hefei 230009 China

Low-power design has become a challenge of test. We propose an effective low-power scan architecture named PowerSluice to minimize power consumption during scan test, which is based on scan chain modifications. On one hand, a kind of blocking logic is inserted into the scan chain to reduce the dynamic power and two kinds of controlling units are also inserted to decrease the leakage power during the shift cycle. On the other hand, using genetic algorithm, the exact values of control signals are found out to control the process. Experiments results indicate that this architecture can effectually reduce power during scan test with probably minimum area cost.

关键词：低功耗设计扫描测试静态测试动态优化合作控制单元电力消耗动态功耗

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