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2006 ACM/IEEE Conference on Supercomputing, SC'06

作者： Tan, Guangming Feng, Shengzhong Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate School Chinese Academy of Sciences

ISBN: (纸本)0769527000

Dynamic programming has been one of the most efficient approaches to sequence analysis and structure prediction in biology. However, their performance is limited due to the drastic increase in both the number of biological data and variety of the computer architectures. With regard to such predicament, this paper creates excellent algorithms aimed at addressing the challenges of improving memory efficiency and network latency tolerance for nonserial polyadic dynamic programming where the dependences are nonuniform. By relaxing the nonuniform dependences, we proposed a new cache oblivious scheme to enhance its performance on memory hierarchy architectures. Moreover we develop and extend a tiling technique to parallelize this nonserial polyadic dynamic programming using an alternate block-cyclic mapping strategy for balancing the computational and memory load, where an analytical parameterized model is formulated to determine the tile volume size that minimizes the total execution time and an algorithmic transformation is used to schedule the tile to overlap communication with computation to further minimize communication overhead on parallel architectures. The numerical experiments were carried out on several high performance computer systems. The new cache-oblivious dynamic programming algorithm achieve 2-10 speedup and the parallel tiling algorithm with communication-computation overlapping shows a desired potential for fine-grained parallel computing on massively parallel computer systems. © 2006 IEEE.

关键词： Dynamic programming

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Integrating DBMSs as a read-only execution layer into Hadoop

Integrating DBMSs as a read-only execution layer into Hadoop

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11th International Conference on Parallel and Distributed computing, Applications and Technologies, PDCAT 2010

作者： An, Mingyuan Wang, Yang Wang, Weiping Sun, Ninghui Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542874

To obtain the efficiency of DBMS, HadoopDB combines Hadoop and DBMS, and claims the superiority over Hadoop in terms of performance. However, the approach of HadoopDB is simply putting MapReduce onto unmodified single-machined DBMSs which has several obvious weaknesses. In essence, HadoopDB is a parallel DBMS with fault tolerance, which incurs unnecessary overhead due to the DBMS legacy. Instead of augmenting DBMS with Hadoop techniques, we propose a new system architecture integrating modified DBMS engines as a read-only execution layer into Hadoop, where DBMS plays a role of providing efficient readonly operators rather than managing the data. Besides the obtained efficiency from DBMS engine, there are other advantages. The modified DBMS engine is able to directly process data from the HDFS (Hadoop Distributed File system) files at the block level, which means that the data replication can be handled by HDFS naturally, and the blocklevel parallelism is easily achieved. The global index access mechanism is added according to the MapReduce paradigm. The data loading speed is also guaranteed by directly writing the data into HDFS with simplified logic. Experiments show that our system outperforms both original Hadoop and HadoopDB styled system. © 2010 IEEE.

关键词： Database systems

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Protein structure prediction based on a domain clustering database

Protein structure prediction based on a domain clustering da...

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2007 1st International Conference on Bioinformatics and Biomedical Engineering, ICBBE

作者： Ma, Zhaoyun Zhang, Fa Xu, Lin Feng, Shengzhong Liu, Zhiyong Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Graduate School Chinese Academy of Sciences

ISBN: (纸本)1424411203

Homology modeling, as a successful protein structure prediction method, has two major deficiencies, i.e., the lack of the templates (known structures), and the accuracy of alignment between the query (unknown structure) and its templates. To solve these problems, we have constructed a conservative domain clustering template database, and proposed a profile-based alignment algorithm based on the profile extracted from each domain clustering in the database. The extracted profile can well represent the information of the sequence and structure as well. Compared with other alignment methods, such as T-coffee and Smith-Water man, our results show that with this method it's possible to obtain a higher hit rate for template searching and a more accurate and reliable query-template alignment. Therefore, the quality of protein structure prediction can be improved. © 2007 Crown Copyright.

关键词： Proteins

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High-efficient architecture of Godson-T many-core processor 23

High-efficient architecture of Godson-T many-core processor

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23rd IEEE Hot Chips Symposium, HCS 2011

作者： Fan, Dongrui Zhang, Hao Wang, Da Ye, Xiaochun Song, Fenglong Zhang, Junchao Fan, Lingjun Advanced Micro-System Group National Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and targeted markets for AMS's Godson-T microprocessor...

ISBN: (纸本)9781467388771

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Efficient Algorithm for Energy-Aware Virtual Network Embedding

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Tsinghua Science and technology 2016年第4期21卷 407-414页

作者： Shuxian Jia Guiyuan Jiang Peilan He Jigang Wu School of Computer Software Technology Zhejiang University Ningbo 315048 China School of Computer Science and Engineering Nanyang Technological University 639798 Singapore State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Network virtualization is a promising approach for resource management that allows customized Virtual Networks （VNs） to be multiplexed on a shared physical infrastructure. A key function that network virtualization can provide is Virtual Network Embedding （VNE）, which maps virtual networks requested by users to a shared substrate network maintained by an Internet service provider. Existing research has worked on this, but has primarily focused on maximizing the revenue of the Internet service provider. In this paper, we consider energy-aware virtual network embedding, which aims at minimizing the energy consumption for embedding virtual networks in a substrate network. In our optimization model, we consider energy consumption of both links and nodes. We propose an efficient heuristic to assign virtual nodes to appropriate substrate nodes based on priority, where existing activated nodes have higher priority for hosting newly arrived virtual nodes. In addition, our proposed algorithm can take advantage of activated links for embedding virtual links so as to minimize total energy consumption. The simulation results show that, for all the cases considered, our algorithm can improve upon previous work by an average of 12.6% on acceptance rate, while the consumed energy can be reduced by 12.34% on average.

关键词： virtualization technology virtual network embedding energy efficient optimization algorithm

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Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations

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Chinese Journal of Electronics 2015年第1期24卷 83-87页

作者： LI Jianwei DONG Gang WANG Zeng YE Xiaochun Faculty of Automation and Information Engineering Xi'an University of Technology State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Microelectronics Institute Xidian University College of Physics Sicence Qingdao University

When operating frequency is over several gigahertz, the effect of inductance plays an important role and should be included for accurate and speed crosstalk noise analysis. And for new generation IC(Integrated circuit) design tools, the crosstalk noise analysis tools should consider the influence of process variations. In this paper, we propose coupled RLC crosstalk noise distributed parameter model with capacitive load termination. And we develop the framework that how to use the crosstalk noise model for process variations. Our results show that compare with HSPICE, the critical data errors of proposed model are within 1% and the relative errors occurred between calculated values for process variations and HSPICE Monte Carlo simulation values are less than 5%. The key features of the new model include:(1) The impact of inductance on crosstalk noise is considered;(2) The model can be used for process variations analysis;(3) The model reflect the effects of load capacitance directly;(4) The numerical inversion of Laplace transform is introduced for improving speed. So the proposed model meets the needs of future IC design both in speed and accuracy.

关键词： Crosstalk noise Interconnect Inductance Process variation Statistical

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Understanding the GPU Microarchitecture to Achieve Bare-Metal Performance Tuning

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ACM SIGPLAN Notices 2017年第8期52卷 31-43页

作者： Zhang, Xiuxia Tan, Guangming Xue, Shuangbai Li, Jiajia Zhou, Keren Chen, Mingyu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China Georgia Institute of Technology United States

In this paper, we present a methodology to understand GPU microarchitectural features and improve performance for compute-intensive kernels. The methodology relies on a reverse engineering approach to crack the GPU ISA encodings in order to build a GPU assembler. An assembly microbenchmark suite correlates microarchitectural features with their performance factors to uncover instruction-level and memory hierarchy preferences. We use SGEMM as a running example to show the ways to achieve bare-metal performance tuning. The performance boost is achieved by tuning FFMA throughput by activating dual-issue, eliminating register bank conflicts, adding non-FFMA instructions with little penalty, and choosing proper width of global/shared load instructions. On NVIDIA Kepler K20m, we develop a faster SGEMM with 3.1Tflop/s performance and 88% efficiency;the performance is 15% higher than cuBLAS7.0. Applying these optimizations to convolution, the implementation gains 39%-62% performance improvement compared with cuDNN4.0. The toolchain is an attempt to automatically crack different GPU ISA encodings and build an assembler adaptively for the purpose of performance enhancements to applications on GPUs. © 2017 ACM.

关键词： Reverse engineering

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IMPULP:A Hardware Approach for In-Process Memory Protection via User-Level Partitioning

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Journal of computer Science & technology 2020年第2期35卷 418-432页

作者： Yang-Yang Zhao Ming-Yu Chen Yu-Hang Liu Zong-Hao Yang Xiao-Jing Zhu Zong-Hui Hong Yun-Ge Guo State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518055China

In recent years many security attacks occur when malicious codes abuse in-process memory *** to the increasing complexity,an application program may call third-party code which cannot be controlled by programmers but may contain security *** a result,the users have the risk of suffering information leakage and control flow ***,current solutions like Intel memory protection extensions(MPX)severely degrade performance,while other approaches like Intel memory protection keys(MPK)lack flexibility in dividing security *** this paper,we propose IMPULP,an effective and efficient hardware approach for in-process memory *** rationale of IMPULP is user-level partitioning that user code segments are divided into different security domains according to their instruction addresses,and accessible memory spaces are specified dynamically for each domain via a set of boundary *** instruction related to memory access will be checked according to its security domain and the corresponding boundaries,and illegal in-process memory access of untrusted code segments will be *** can be leveraged to prevent a wide range of in-process memory abuse attacks,such as buffer overflows and memory *** verification,an FPGA prototype based on RISC-V instruction set architecture has been *** present eight tests to verify the effectiveness of IMPULP,including five memory protection function tests,a test to defense typical buffer overflow,a test to defense famous memory leakage attack named Heartbleed,and a test for security *** execute the SPEC CPU2006 benchmark programs to evaluate the efficiency of *** performance overhead of IMPULP is less than 0.2%runtime on average,which is ***,the resource overhead is less than 5.5%for hardware modification of IMPULP.

关键词： in-process isolation memory protection out-of-bounds user-level partitioning

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A decomposition based algorithm for maximal contractions

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Frontiers of computer Science 2013年第6期7卷 801-811页

作者： Dongchen JIANG Wei LI Jie LUO Yihua LOU Zhengzhong LIAO State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China State Key Laboratory of Software Development Environment Beihang University Beijing 100191 China Tencent Technology (Beijing) Company Limited Beijing 100080 China

This paper proposes a decomposition based algo- rithm for revision problems in classical propositional logic. A set of decomposing rules are presented to analyze the satis- fiability of formulas. The satisfiability of a formula is equivalent to the satisfiability of a set of literal sets. A decomposing function is constructed to calculate all satisfiable literal sets of a given formula. When expressing the satisfiability of a formula, these literal sets are equivalent to all satisfied models of such formula. A revision algorithm based on this decomposing function is proposed, which can calculate maximal contractions of a given problem. In order to reduce the memory requirement, a filter function is introduced. The improved algorithm has a good performance in both time and space perspectives.

关键词： belief change maximal contraction decomposing rules revision algorithm

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Software and hardware co-designed multi-level TLBs for chip multiprocessors

Software and hardware co-designed multi-level TLBs for chip ...

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11th IEEE International Conference on computer and Information technology, CIT 2011 and 11th IEEE International Conference on Scalable computing and Communications, SCALCOM 2011

作者： Zhang, Xiaohui Cong, Ming Chen, Guangqiang Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University Beijing China National University of Defense Technology Changsha China

ISBN: (纸本)9780769543888

Translation Lookaside Buffers ( TLBs ) have a significant impact on system performance. Numerous prior studies focus on TLBs design for uniprocessors. With the advent of chip multiprocessors (CMPs), we need a shift to TLBs for chip multiprocessors. This paper presents a software-implemented level-two TLB-SL2-TLB which is a shared level-two TLB for multiprocessors. It not only reduces the cost of TLB refill handler for every processor core, but also reduces the redundant TLB misses' cost for CMPs effectively. Today, CMPs typically employ private per-core TLBs. SL2-TLB together with the hardware TLBs make up a software-hardware co-designed multilevel TLB system which brings great benefit to system performance while avoiding changing the hardware TLB. So it is a convenient and efficient method for CMPs' TLB performance improvement. The benefit brought by SL2-TLB to SPECCPU2000 is less than that to SPECCPU2006, about 5% and 7% separately. Thereinto, the average performance improvement of SPECint 2006 reaches about 12.7%. That is because the overhead for TLB refill is small when the cache is large enough to avoid a miss as walking the page table of applications with small memory footprints. The further optimization for SL2-TLB is kept the SL2-TLB table stay in L2 cache forever by the cache locking scheme. SL2-TLB together with cache locking scheme improves the performances by over 13% for SPECint 2006. And an average performance improvement of over 7% is brought to the new emerging parallel benchmark suite- Princeton Application Repository for Shared-Memory computers (PARSEC). And all the above evaluations are done on Godson-3 processors which is the latest generation of China's most powerful microprocessor family. © 2011 IEEE.

关键词： Benchmarking

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