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IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Xiaochun, Ye Dongrui, Fan Wei, Lin Key Lab of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Exact pairwise sequence alignment algorithms using dynamic programming require quadratic space and time, and this makes these algorithms impractical for large-scale sequences. In this paper, we propose and evaluate a new Anti-Diagonal based Parallel Linear-Space Algorithm (AD-PLSA). It records similarity matrix scores and start points on special anti-diagonals instead of special rows or columns. This algorithm is able to further reduce the total amount of re-computation. It also produces balanced sub-problems with approximately even size, and this is of great benefit to the parallelization. In addition, we establish a dynamic parallelization framework for the efficient acceleration on a symmetric multiprocessor (SMP) platform. The experimental results present liner speedup for long real DNA sequences. Compared with the typical row-col algorithm, our method is able to save more than 30% of the re-computation, and run twice as fast in the backward phase. © 2009 IEEE.

关键词： DNA sequences

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Macro liveness graph and liveness of ω-independent unbounded nets

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Science China(Information Sciences) 2015年第3期58卷 132-141页

作者： WANG ShouGuang GAN MengDi ZHOU MengChu School of Information and Electronic Engineering Zhejiang Gongshang University Key Laboratory of Embedded System and Service Computing Ministry of EducationTongji University Department of Electrical and Computer Engineering New Jersey Institute of Technology

Liveness is a basic property of a system and the liveness issue of unbounded Petri nets remains one of the most difficult problems in this *** work proposes a novel method to decide the liveness of a class of unbounded generalized Petri nets calledω-independent unbounded nets,breaking the existing limits to one-place-unbounded *** algorithm to construct a macro liveness graph(MLG)is developed and a critical condition based on MLG deciding the liveness ofω-independent unbounded nets is *** are provided to demonstrate its effectiveness.

关键词： discrete event system(DES) Petri nets complex systems liveness property analysis

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DLPlib： A Library for Deep Learning Processor

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Journal of computer Science & technology 2017年第2期32卷 286-296页

作者： Hui-Ying Lan Lin-Yang Wu Xiao Zhang Jin-Hua Tao Xun-Yu Chen Bing-Rui Wang Yu-Qing Wang Qi Guo Yun-Ji Chen State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Microprocessor Research Center Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China Department of Computer Science University of Science and Technology of China Hefei 230026 China

Recently, deep learning processors have become one of the most promising solutions of accelerating deep learning algorithms. Currently, the only method of programming the deep learning processors is through writing assembly instructions by bare hands, which costs a lot of programming efforts and causes very low efficiency. One solution is to integrate the deep learning processors as a new back-end into one prevalent high-level deep learning framework （e.g., TPU （tensor processing unit） is integrated into Tensorflow directly）. However, this will obstruct other frameworks to profit from the programming interface, The alternative approach is to design a framework-independent low-level library for deep learning processors （e.g., the deep learning library for GPU, cuDNN）. In this fashion, the library could be conveniently invoked in high-level programming frameworks and provides more generality. In order to allow more deep learning frameworks to gain benefits from this environment, we envision it as a low-level library which could be easily embedded into current high-level frameworks and provide high performance. Three major issues of designing such a library are discussed. The first one is the design of data structures. Data structures should be as few as possible while being able to support all possible operations. This will allow us to optimize the data structures easier without compromising the generality. The second one is the selection of operations, which should provide a rather wide range of operations to support various types of networks with high efficiency. The third is the design of the API, which should provide a flexible and user-friendly programming model and should be easy to be embedded into existing deep learning frameworks. Considering all the above issues, we propose DLPIib, a tensor-filter based library designed specific for deep learning processors. It contains two major data structures, tensor and filter, and a set of operators including basic neur

关键词： deep learning processor API library DLPlib

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Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor systems of Cluster Platforms

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Journal of computer Science & technology 2014年第1期29卷 21-37页

作者：吕方崔慧敏王蕾刘磊武成岗冯晓兵游本中 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences CCF ACM IEEE Department of Computer Science and Engineering University of Minnesota at Twin Cities Institute of Information Science Academia Sinica

Efficiency of batch processing is becoming increasingly important for many modern commercial service centers, e.g., clusters and cloud computing datacenters. However, periodical resource contentions have become the major performance obstacles for concurrently running applications on mainstream CMP servers. I/O contention is such a kind of obstacle, which may impede both the co-running performance of batch jobs and the system throughput seriously. In this paper, a dynamic I/O-aware scheduling algorithm is proposed to lower the impacts of I/O contention and to enhance the co-running performance in batch processing. We set up our environment on an 8-socket, 64-core server in Dawning Linux Cluster. Fifteen workloads ranging from 8 jobs to 256 jobs are evaluated. Our experimental results show significant improvements on the throughputs of the workloads, which range from 7% to 431%. Meanwhile, noticeable improvements on the slowdown of workloads and the average runtime for each job can be achieved. These results show that a well-tuned dynamic I/O-aware scheduler is beneficial for batch-mode services. It can also enhance the resource utilization via throughput improvement on modern service platforms.

关键词： chip multiprocessor batch processing co-running I/0 contention scheduling

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Statistical static timing analysis for circuit aging prediction

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The Journal of China Universities of Posts and Telecommunications 2021年第2期28卷 14-23页

作者： Duan Shengyu Zhai Dongyao Lu Yue Shanghai Engineering Research Center of Intelligent Computing System Shanghai UniversityShanghai 200444China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Electronics and Computer Science University of SouthamptonSouthamptonUK

Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit *** results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic *** amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design *** this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI *** consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability *** method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.

关键词： bias temperature instability(BTI) reliability prediction statistical static timing analysis(SSTA)

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Sampling Methods for Efficient Training of Graph Convolutional Networks:A Survey

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IEEE/CAA Journal of Automatica Sinica 2022年第2期9卷 205-234页

作者： Xin Liu Mingyu Yan Lei Deng Guoqi Li Xiaochun Ye Dongrui Fan State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100086 School of Computer Science and Technology University of Chinese Academy of SciencesBeijing 100049 IEEE Department of Precision Instrument Center for Brain Inspired Computing ResearchTsinghua UniversityBeijing 100084China

Graph convolutional networks(GCNs)have received significant attention from various research fields due to the excellent performance in learning graph *** GCN performs well compared with other methods,it still faces *** a GCN model for large-scale graphs in a conventional way requires high computation and storage ***,motivated by an urgent need in terms of efficiency and scalability in training GCN,sampling methods have been proposed and achieved a significant *** this paper,we categorize sampling methods based on the sampling mechanisms and provide a comprehensive survey of sampling methods for efficient training of *** highlight the characteristics and differences of sampling methods,we present a detailed comparison within each category and further give an overall comparative analysis for the sampling methods in all ***,we discuss some challenges and future research directions of the sampling methods.

关键词： Efficient training graph convolutional networks(GCNs) graph neural networks(GNNs) sampling method

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Identity-Based key-Insulated Proxy Signature Without Random Oracles

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Journal of Shanghai Jiaotong university(Science) 2011年第5期16卷 557-566页

作者：陈剑洪龙宇陈克非王永涛 Department of Computer Science and Engineering Shanghai Jiaotong University School of Computer Engineering Huaiyin Institute of Technology Shanghai Key Laboratory of Scalable Computing and System Shanghai Jiaotong University

In an identity based proxy signature (IBPS) scheme, a designated proxy signer can generate the signature on behalf of an original signer. Traditional IBPS schemes normally rely on the assumption that private keys are kept perfectly secure. However, due to viruses, worms or other break-ins allowed by operating-system holes, key exposure seems inevitable. To minimize the damage caused by key exposure in IBPS, we propose an identity-based key-insulated proxy signature (IBKIPS) scheme in the standard model, i.e. without random oracles.

关键词： key-insulated proxy signature identity-based standard model

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Extended selective encoding of scan slices for reducing test data and test power

Extended selective encoding of scan slices for reducing test...

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作者： Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Sciences China School of Computer and Information Hefei University of Technology China

Test data volume and test power are two major concerns when testing modern large circuits. Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying a single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques to optimize this method: a flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy can decrease the number of groups which need to be encoded and improve test data compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 25.6% and peak weighted switching activity by 9.68% during scan shift compared to selective encoding. Copyright © 2010 The institute of Electronics, Information and Communication Engineers.

关键词： Filling

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FlexPDA:A Flexible Programming Framework for Deep Learning Accelerators

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Journal of computer Science & technology 2022年第5期37卷 1200-1220页

作者： Lei Liu Xiu Ma Hua-xiao Liu Guang-li Li Lei Liu College of Computer Science and Technology Jilin UniversityChangchunChina Key Laboratory of Symbolic Computation and Knowledge Engineering of Ministry of Education Jilin UniversityChangchunChina State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijingChina University of Chinese Academy of Sciences BeijingChina

There are a wide variety of intelligence accelerators with promising performance and energy efficiency,deployed in a broad range of applications such as computer vision and speech ***,programming productivity hinders the deployment of deep learning *** low-level library invoked in the high-level deep learning framework which supports the end-to-end execution with a given model,is designed to reduce the programming burden on the intelligence ***,it is inflexible for developers to build a network model for every deep learning application,which probably brings unnecessary repetitive *** this paper,a flexible and efficient programming framework for deep learning accelerators,FlexPDA,is proposed,which provides more optimization opportunities than the low-level library and realizes quick transplantation of applications to intelligence accelerators for fast *** evaluate FlexPDA by using 10 representative operators selected from deep learning algorithms and an end-to-end *** experimental results validate the effectiveness of FlexPDA,which achieves an end-to-end performance improvement of 1.620x over the low-level library.

关键词： deep learning accelerator programming framework domain-specific language

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A survey of routing algorithm for mesh Network-on-Chip

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Frontiers of computer Science 2016年第4期10卷 591-601页

作者： Yue WU Chao LU Yunji CHEN State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 101408 China Loongson Technology Corporation Limited Beijing 100095 China

With the rapid development of semiconductor in- dustry, the number of cores integrated on chip increases quickly, which brings tough challenges such as bandwidth, scalability and power into on-chip interconnection. Under such background, Network-on-Chip （NoC） is proposed and gradually replacing the traditional on-chip interconnections such as sharing bus and crossbar. For the convenience of physical layout, mesh is the most used topology in NoC design. Routing algorithm, which decides the paths of pack- ets, has significant impact on the latency and throughput of network. Thus routing algorithm plays a vital role in a wellperformed network. This study mainly ：focuses on the routing algorithms of mesh NoC. By whether taking network information into consideration in routing decision, routing algorithms of NoC can be roughly classified into oblivious routing and adaptive routing. Oblivious routing costs less without adaptiveness while adaptive routing is on the contrary. To combine the advantages of oblivious and adaptive routing algorithm, half-adaptive algorithms were proposed. In this paper, the concepts, taxonomy and features of routing algorithms of NoC are introduced. Then the importance of routing algorithms in mesh NoC is highlighted, and representative routing algorithms with respective features are reviewed and summarized. Finally, we try to shed light upon the future work of NoC routing algorithms.

关键词： Network-on-Chip mesh topology routing algorithm adaptive routing oblivious routing

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