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12th Annual IEEE International Symposium on Network computing and Applications, NCA 2013

作者： Shi, Yangguang Zhang, Fa Liu, Zhiyong Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9780768550436

Energy efficiency is becoming an important issue in networks. Although some research works have been devoted to this topic, only a little attention has been paid to the stability of the network equipped with the energy conservation mechanisms. In fact, we find that the stability of networks can be undermined in the worst case if it isn't considered with care by the energy conservation *** this paper, we propose an energy-efficient scheduling protocol which can guarantee the stability of the network in all cases. We start by building a new model which can be used to verify the stability of the network equipped with the energy conservation mechanisms. With this model, we transform the packet scheduling problem to a Job Shop Scheduling problem. For this problem, we propose a time-stamp based work-conserving scheduling algorithm - G-FSA. Compared with existing methods, this scheduling algorithm guarantees a tighter bound on the make span of the jobs. Then, we integrate G-FSA with a time partition approach to generate our energy-efficient packet scheduling protocol. It is proved that the obtained protocol can guarantee the stability of network in all cases. And its approximation ratio in terms of energy efficiency can be bounded by O((1+ )) for any > 0, where is an input parameter depending on the hardware infrastructure. Typically, 1

关键词： Scheduling algorithms

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Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack

Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA So...

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2017 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2017

作者： Ye, Jing Gong, Yue Hu, Yu Li, Xiaowei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781538614211

Physical Unclonable Function (PUF) is a promising hardware security primitive. However, it is severely threatened by modeling attacks. This paper proposes a novel Polymorphic PUF for CPU+FPGA SoC. We fully exploit the dynamic reconfigurability of the SoC and use the partial reconfiguration bitstream as the challenge to minimize the Challenge Response Pair (CRP) correlation so as to resist modeling attacks. An asymmetric RO pair is proposed to produce the response. Experiments on real CPU+FPGA SoCs show the high resistance of Polymorphic PUF against modeling attacks, with good uniformity and uniqueness. © 2017 IEEE.

关键词： system-on-chip

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Kinematics and Dynamics Analysis of a Quadruped Walking Robot with Parallel Leg Mechanism

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Chinese Journal of Mechanical Engineering 2013年第5期26卷 881-891页

作者： WANG Hongbo SANG Lingfeng HU Xing ZHANG Dianfan YU Hongnian Parallel Robot and Mechatronic System Laboratory of Hebei Province Yanshan University Key Laboratory of Advanced Forging & Stamping Technology and Science of Ministry of Education Yanshan University Xi’an University of Architecture and Technology Science and Technology Research Institute Yanshan University School of Design Engineering and ComputingBournemouth University

It is desired to require a walking robot for the elderly and the disabled to have large capacity,high stiffness,stability,***,the existing walking robots cannot achieve these requirements because of the weight-payload ratio and simple ***,Improvement of enhancing capacity and functions of the walking robot is an important research *** to walking requirements and combining modularization and reconfigurable ideas,a quadruped/biped reconfigurable walking robot with parallel leg mechanism is *** proposed robot can be used for both a biped and a quadruped walking *** kinematics and performance analysis of a 3-UPU parallel mechanism which is the basic leg mechanism of a quadruped walking robot are conducted and the structural parameters are *** results show that performance of the walking robot is optimal when the circumradius R,r of the upper and lower platform of leg mechanism are 161.7 mm,57.7 mm,*** on the optimal results,the kinematics and dynamics of the quadruped walking robot in the static walking mode are derived with the application of parallel mechanism and influence coefficient theory,and the optimal coordination distribution of the dynamic load for the quadruped walking robot with over-determinate inputs is analyzed,which solves dynamic load coupling caused by the branches’ constraint of the robot in the walk *** laying a theoretical foundation for development of the prototype,the kinematics and dynamics studies on the quadruped walking robot also boost the theoretical research of the quadruped walking and the practical applications of parallel mechanism.

关键词： walking robot parallel leg mechanism kinematics dynamics over-determinate inputs

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Exploiting SIMD for complex numerical predicates 32

Exploiting SIMD for complex numerical predicates

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32nd IEEE International Conference on Data Engineering Workshops, ICDEW 2016

作者： Song, Dongxiao Chen, Shimin State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781509021086

We study the use of SIMD instructions to support complex conjunctive numerical predicates. Compared to previous studies, we aim to model more realistic use scenarios, where different data types, different comparison operations, and different predicate types can be mixed in a single filtering clause. Moreover, the evaluation of the predicates on a set of columns can take advantage of multiple processor cores for maximum speed. We find that the diversity of the predicates and the introduction of multiple threads pose significant challenges in modeling and optimizing complex predicates. We propose a code framework based on three alternative SIMD algorithms for conjunctive predicates. Then, we investigate cost models for both single-threaded and multi-threaded evaluation of filtering predicates. Our experimental results on synthetic data show that an optimal SIMD plan can achieve up to 10.4× speedup over the best no SIMD plan, and up to 6.8× speedup over sub-optimal SIMD plans. © 2016 IEEE.

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P-GAS: Parallelizing a cycle-accurate event-driven many-core processor simulator using parallel discrete event simulation 10

P-GAS: Parallelizing a cycle-accurate event-driven many-core...

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24th Annual Workshop on Principles of Advanced and Distributed Simulation, PADS 2010

作者： Lv, Huiwei Cheng, Yuan Bai, Lu Chen, Mingyu Fan, Dongrui Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School Chinese Academy of Sciences China

ISBN: (纸本)9781424472918

Multi-core processors are commonly available now, but most traditional computer architectural simulators still use single-thread execution. In this paper we use parallel discrete event simulation (PDES) to speedup a cycle-accurate event-driven many-core processor simulator. Evaluation against the sequential version shows that the parallelized one achieves an average speedup of 10.9× (up to 13.6×) running SPLASH-2 kernel on a 16-core host machine, with cycle counter differences of less than 0.1%. Moreover, super-linear speedups are achieved between running 1 thread and 8 threads due to reduced overhead of insert-event-to-queue time and increased cache size in parallel processing. We conclude that PDES could be an attractive option for achieving fast cycle-accurate many-core processor simulations. © 2010 IEEE.

关键词： Simulators

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STEED: An analytical database system for TrEE-structured data 43

STEED: An analytical database system for TrEE-structured dat...

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43rd International Conference on Very Large Data Bases, VLDB 2017

作者： Wang, Zhiyi Zhou, Dongyan Chen, Shimin State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

Tree-structured data formats, such as JSON and Protocol Buffers, are capable of expressing sophisticated data types, including nested, repeated, and missing values. While such expressing power contributes to their popularity in real-world applications, it presents a significant challenge for systems supporting tree-structured data. Existing systems have focused on general-purpose solutions either extending RDBMSs or designing native systems. However, the general-purpose approach often results in sophisticated data structures and algorithms, which may not reflect and optimize for the actual structure patterns in the real world. In this demonstration, we showcase Steed, an analytical database system for tree-structured data. We use the insights gained by analyzing representative real-world tree structured data as guidelines in the design of Steed. Steed learns and extracts a schema tree for a data set and uses the schema tree to reduce the storage space and improve the efficiency of data field accesses. We observe that sub-structures in real world data are often simple, while the treestructured data types can support very sophisticated structures. We optimize the storage structure, the column assembling algorithm, and the in-memory layout for the simple sub-structures (a.k.a. simple paths). Compared to representative state-of-the-art systems (i.e. PostgreSQL/JSON, MongoDB, and Hive+Parquet), Steed achieves orders of magnitude better performance for data analysis queries. © 2017 VLDB Endowment.

关键词： Database systems

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A Non-Stop Double Buffering Mechanism for Dataflow architecture

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Journal of computer Science & technology 2018年第1期33卷 145-157页

作者： Xu Tan Xiao-Wei Shen Xiao-Chun Ye Da Wang Dong-Rui Fan Lunkai Zhang Wen-Ming Li Zhi-Min Zhang Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 100049 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125 China Department of Computer Science The University of Chicago Chicago IL 60637 U.S.A.

Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataftow architecture achieves a 16.2% average efficiency improvement over that without the optimization.

关键词： non-stop double buffering dataflow architecture high-performance computing

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Beyond green: Evolution to adaptability and recyclability

Beyond green: Evolution to adaptability and recyclability

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2011 IEEE/ACM International Conference on Green computing and Communications, GreenCom 2011

作者： Sun, Yuzhong Song, Ying Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769544663

In current social computing system, not only hardware but also software experiences a directly discarded mode. Such directly discarded mode may result in huge waste. The major challenge in green computing is the recyclability of the computing system. In order to address this challenge in the software field, this paper proposes a design idea of green software embodying the adaptability and recyclability. The adaptable and recyclable strategy may consist of two phases. The first one is compressing the increasingly deeper software stack;another one is keeping the functionality recycling and code reuse. The adaptability and recyclability mean automatically decomposing the complex software into several parts which are ease to be reused and automatically selecting the feasible parts for the on-writing software. And we also explore the system software design path to adaptability and recyclability in our previous work as well as in the future. © 2011 IEEE.

关键词： Software design

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A novel post-silicon debug mechanism based on Suspect Window

A novel post-silicon debug mechanism based on Suspect Window

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作者： Gao, Jianliang Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Beijing China

Bugs are becoming unavoidable in complex integrated circuit design. It is imperative to identify the bugs as soon as possible through post-silicon debug. For post-silicon debug, observability is one of the biggest challenges. Scan-based debug mechanism provides high observability by reusing scan chains. However, it is not feasible to scan dump cycle-by-cycle during program execution due to the excessive time required. In fact, it is not necessary to scan out the error-free states. In this paper, we introduce Suspect Window to cover the clock cycle in which the bug is triggered. Then, we present an efficient approach to determine the suspect window. Based on Suspect Window, we propose a novel debug mechanism to locate the bug both temporally and spatially. Since scan dumps are only taken in the suspect window with the proposed mechanism, the time required for locating the bug is greatly reduced. The approaches are evaluated using ISCAS'89 and ITC'99 benchmark circuits. The experimental results show that the proposed mechanism can significantly reduce the overall debug time compared to scan-based debug mechanism while keeping high observability. Copyright © 2010 The institute of Electronics, Information and Communication Engineers.

关键词： Observability

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Optimizing Multi-Dimensional Packet Classification for Multi-Core systems

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Journal of computer Science & technology 2018年第5期33卷 1056-1071页

作者： Tong Shen Da-Fang Zhang Gao-Gang Xie Xin-Yi Zhang College of Computer Science and Electronic Engineering Hunan University Changsha 410082 China Network Technology Research Center Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

Packet classification has been studied for decades; it classifies packets into specific flows based on a given rule set. As software-defined network was proposed, a recent trend of packet classification is to scale the five-tuple model to multi-tuple. In general, packet classification on multiple fields is a complex problem. Although most existing software-based algorithms have been proved extraordinary in practice, they are only suitable for the classic five-tuple model and difficult to be scaled up. Meanwhile, hardware-specific solutions are inflexible and expensive, and some of them are power consuming. In this paper, we propose a universal multi-dimensional packet classification approach for multi-core systems. In our approach, novel data structures and four decomposition-based algorithms are designed to optimize the classification and updating of rules. For multi-field rules, a rule set is cut into several parts according to the number of fields. Each part works independently. In this way, the fields are searched in parallel and all the partial results are merged together at last. To demonstrate the feasibility of our approach, we implement a prototype and evaluate its throughput and latency. Experimental results show that our approach achieves a 40% higher throughput than that of other decomposed-based algorithms and a 43% lower latency of rule incremental update than that of the other algorithms on average. Furthermore, our approach saves 39% memory consumption on average and has a good scalability.

关键词： multi-dimensional multi-core packet classification

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