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2011 7th International Conference on Natural Computation, ICNC 2011

作者： Chen, Long Huo, Wei Mi, Haitao Zhang, Zhaoqing Feng, Xiaobing Li, Zhiyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Purdue University West Lafayette IN 47907 United States

ISBN: (纸本)9781424499533

Machine translation (MT), with its broad potential use, has gained increased attention from both researchers and software vendors. To generate high quality translations, however, MT decoders can be highly computation intensive. With significant raw computing power, multi-core microprocessors have the potential to speed up MT software on desktop machines. However, retrofitting existing MT decoders is a nontrivial issue. Race conditions and atomicity issues are among those complications making parallelization difficult. In this article, we show that, to parallelize a state-of-the-art MT decoder, it is much easier to overcome such difficulties by using a process-based parallelization method, called functional task parallelism, than using conventional thread-based methods. We achieve a 7.60 times speed up on an 8-core desktop machine while making significantly less changes to the original sequential code than required by using multiple threads. © 2011 IEEE.

关键词： Machine translation

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Labeled Network Stack: A High-Concurrency and Low-Tail Latency Cloud Server Framework for Massive IoT Devices

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Journal of computer Science & technology 2020年第1期35卷 179-193页

作者： Wen-Li Zhang Ke Liu Yi-Fan Shen Ya-Zhu Lan Hui Song Ming-Yu Chen Yuan-Fei Chen State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518000China Zhongke Zhicheng Electronic Technology Company Limited Jining 272000China

Internet of Things(IoT)applications have massive client connections to cloud servers,and the number of networked IoT devices is remarkably *** services require both low-tail latency and high concurrency in *** study aims to determine whether an order of magnitude improvement is possible in tail latency and concurrency in mainstream systems by proposing a hardware-software codesigned labeled network stack(LNS)for future *** key innovation is a cross-layered payload labeling mechanism that distinguishes different requests by payload across the full network stack,including application,TCP/IP,and Ethernet *** type of design enables prioritized data packet processing and forwarding along the full datapath,such that latency-insensitive requests cannot significantly interfere with high-priority *** build a prototype datacenter server to evaluate the LNS design against a commercial X86 server and the mTCP research,using a cloud-supported IoT application *** results show that the LNS design can provide an order of magnitude improvement in tail latency and concurrency.A single datacenter server node can support over 2 million concurrent long-living connections for IoT devices as a 99-percentile tail latency of 50 ms is *** addition,the hardware-software codesign approach remarkably reduces the labeling and prioritization overhead and constrains the interference of high-priority requests to low-priority requests.

关键词： tail latency high concurrency network stack cloud server Internet of Things(IoT)service

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Multi‐granularity re‐ranking for visible‐infrared person re‐identification

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CAAI Transactions on Intelligence technology 2023年第3期8卷 770-779页

作者： Yadi Wang Hongyun Zhang Duoqian Miao Witold Pedrycz Department of Computer Science and Technology Tongji UniversityShanghaiChina Key Laboratory of Embedded System and Service Computing Ministry of EducationShanghaiChina Department of Electrical and Computer Engineering University of AlbertaEdmontonAlbertaCanada System Research Institute Polish Academy of SciencesWarsawPoland

Visible‐infrared person re‐identification(VI‐ReID)is a supplementary task of single‐modality re‐identification,which makes up for the defect of conventional re‐identification under insufficient *** is more challenging than single‐modality ReID because,in addition to difficulties in pedestrian posture,camera shoot-ing angle and background change,there are also difficulties in the cross‐modality *** works only involve coarse‐grained global features in the re‐ranking calculation,which cannot effectively use fine‐grained ***,fine‐grained features are particularly important due to the lack of information in cross‐modality re‐*** this end,the Q‐center Multi‐granularity K‐reciprocal Re‐ranking Algorithm(termed QCMR)is proposed,including a Q‐nearest neighbour centre encoder(termed QNC)and a Multi‐granularity K‐reciprocal Encoder(termed MGK)for a more comprehensive feature *** converts the probe‐corresponding modality features into gallery corresponding modality features through modality transfer to narrow the modality *** takes a coarse‐grained mutual nearest neighbour as the dominant and combines a fine‐grained nearest neighbour as a supplement for similarity *** experiments on two widely used VI‐ReID benchmarks,SYSU‐MM01 and RegDB have shown that our method achieves state‐of‐the‐art ***,the mAP of SYSU‐MM01 is increased by 5.9%in all‐search mode.

关键词： computer vision recognition

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A study and implementation of the Huffman algorithm based on condensed Huffman table

A study and implementation of the Huffman algorithm based on...

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International Conference on computer Science and Software Engineering, CSSE 2008

作者： Bao, Ergude Li, Weisheng Fan, Dongrui Ma, Xiaoyu School of Software Beijing Jiaotong University Key Laboratory of Computer System and Architecture Institute of Computer Technology Chinese Academy of Sciences

ISBN: (纸本)9780769533360

Huffman codes are being widely used as a very efficient technique for compressing data. To achieve high compressing ratio, some properties of encoding and decoding for canonical Huffman table are discussed. A study and implementation of the Huffman algorithm based on condensed Huffman table is studied. New condensed Huffman table could reduce the cost of the Huffman coding table. Compared with traditional Huffman coding table and other improved tables, the best advantages of new condensed Huffman table is that the space requirement is reduced significantly. © 2008 IEEE.

关键词： Codes (symbols)

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Evaluating and Constraining Hardware Assertions with Absent Scenarios

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Journal of computer Science & technology 2020年第5期35卷 1198-1216页

作者： Hui-Na Chao Hua-Wei Li Xiaoyu Song Tian-Cheng Wang Xiao-Wei Li State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518052China Department of Electrical and Computing Engineering Portland State UniversityPortlandOR 97207U.S.A.

Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion *** the simulation data is inherently incomplete,it is necessary to evaluate the truth values of the mined *** paper presents an approach to evaluating and constraining hardware assertions with absent scenarios.A Belief-fail Rate metric is proposed to predict the truth/falseness of generated *** considering both the occurrences of free variable assignments and the conflicts of absent scenarios,we use the metric to sort true assertions in higher ranking and false assertions in lower *** Belief-failRate guided assertion constraining method leverages the quality of generated *** experimental results show that the Belief-failRate framework performs better than the existing *** addition,the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.

关键词： hardware formal verification assertion generation data mining assertion evaluation assertion coverage

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Fast path selection for testing of small delay defects considering path correlations

Fast path selection for testing of small delay defects consi...

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28th IEEE VLSI Test Symposium, VTS10

作者： He, Zijian Lv, Tao Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of the Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424466481

Statistical timing models have been proposed to describe delay variations in very deep sub-micro process technologies, which have increasingly significant influence on circuit performance. Under a statistical timing model, testing of a path can detect potential delay failures caused by different small delay defects. Due to path correlations, the potential delay failures captured by two different paths overlap between each other more or less. It is difficult to find a given number of paths that can capture most potential delay failures. In this paper, the path selection problem is converted to a minimal space intersection problem, and a greedy path selection heuristics is proposed, the key point of which is to calculate the probability that the paths in a specified path set all meet the delay constraint. Statistical timing analysis technologies and heuristics are used in the calculation. Experimental results show that the proposed approach is time-efficient and achieves a higher probability of capturing delay failures in comparison with conventional path selection approaches. ©2010 IEEE.

关键词： Defects

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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

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2007 IEEE International Test Conference, ITC

作者： Wang, Da Fan, Xiaoxin Fu, Xiang Liu, Hui Wen, Ke Li, Rui Li, Huawei Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Beijing China Co. Ltd. Shanghai China

ISBN: (纸本)1424411289

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals. © 2007 IEEE.

关键词： Design for testability

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GVE: Godson-T verification engine for many-core architecture rapid prototyping and debugging

GVE: Godson-T verification engine for many-core architecture...

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2010 International Conference on Field-Programmable technology, FPT'10

作者： Lei, Zhengmeng Zhang, Lunkai Song, Fenglong Tang, Shibin Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424489817

In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5 LX330 FPGAs, thus permitting us to map our many-core processor and peripheral devices into it. Besides the hardware, our toolkit Godson-T Studio provides the compiler, program loader, debugger and monitor to fulfil the purpose of developing, profiling and debugging, while the accuracy loss problem is settled by our novel techniques: Check-point and ILA-Check, presented in this paper. To our experience, GVE greatly reduces the verification cycle due to its high execution speed, for example, it finishes thousands of testcases in an hour, where the software-based approach takes few days to run. And by the help of the checkpoint framework, we can easily locate the faults. Because of these features, GVE makes a great contribution to the 16-tile Godson-T tape-out Project. © 2010 IEEE.

关键词： Verification

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Cacheap:Portable and Collaborative I/O Optimization for Graph Processing

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Journal of computer Science & technology 2019年第3期34卷 690-706页

作者： Peng Zhao Chen Ding Lei Liu Jiping Yu Wentao Han Xiao-Bing Feng State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Department of Computer Science University of RochesterRochester 14623U.S.A. Department of Computer Science and Technology Tsinghua UniversityBeijing 100084China

Increasingly there is a need to process graphs that are larger than the available memory on today's *** systems have been developed with grapli representations that are efficient and compact for out-of-core processing.A necessary task in these systems is memory *** paper presents a system called Cacheap which automatically and efficiently manages the available memory to maximize the speed of grapli processing,minimize the amount of disk access,and maximize the utilization of memory for graph *** has a simple interface that can be easily adopted by existing graph *** paper describes the new system,uses it in recent graph engines,and demonstrates its integer factor improvements in the speed of large-scale grapli processing.

关键词： out-of-core graph processing system I/O optimization memory cache graph analytics locality

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Deterministic Circular Self Test Path

Deterministic Circular Self Test Path

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第十二届全国容错计算学术会议

作者： WEN Ke HU Yu LI Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100％ fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

关键词： very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic

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