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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Shijian Zhang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

Conventional temporal redundant techniques to detect transient faults have resulted in considerable performance loss. One major reason for this problem is the reclamation of some critical resources, such as the instruction window and physical registers, is delayed, which degrades instruction-level parallelism. This paper proposes a novel fault- tolerant micro-architecture based on checkpoint mechanism. All occupied resources are reclaimed during the retirement stage in the first execution. Therefore, the performance overhead is mitigated evidently. Our scheme requires only small hardware cost and provides short fault detection latency.

关键词： Registers Fault detection Retirement Hardware Costs Delay Pipelines Buffer storage Redundancy Yarn

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A new dynamic method of machine learning from transition examples

Journal of Software

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Journal of Software 2011年第10期6卷 2064-2067页

作者： Zhang, Xiao-Dan Zhang, De-Gan Zhao, De-Xin Kang, Xue-Jing Qiao, Xiao-Dong Institute of Scientific and Technical Information of China Beijing 100038 China Tianjin Key Lab of Intelligent Computing and Novel software Technology Tianjin University of Technology China Key Laboratory of Computer Vision and System Tianjin University of Technology China

It's well known machine learning from examples is an effective method to solve non-linear classification problem. A new dynamic method of machine learning from transition example is given in this paper. This method can improve the traditional method ID3 which learns from static eigenvalues of examples. The limits of the traditional method ID3 lie on no comprehension and no memory, especially, no the varieties and dynamic correlation of eigenvalues. In the new method, it can learn from dynamic eigenvalues, the change of data can be learned because the training data is the initial eigenvalue and the end eigenvalue in the interval. All eigenvalue's varieties and correlation can be understood and remembered in application. By test experiments, the new method can be used as classifier when the multi-parameters are dynamic correlation, and it has special use in the many kinds of information fusion fields. © 2011 ACADEMY PUBLISHER.

关键词： Classification (of information)

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An Efficient Threshold key-Insulated Signature Scheme

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Journal of Shanghai Jiaotong university(Science) 2011年第6期16卷 658-662页

作者：陈剑洪龙宇陈克非王永涛李祥学 Department of Computer Science and Engineering Shanghai Jiaotong University School of Computer Engineering Huaiyin Institute of Technology Shanghai Key Laboratory of Scalable Computing and System Shanghai Jiaotong University Department of Computer Science and Technology East China Normal University

To tackle the key-exposure problem in signature settings,this paper introduces a new cryptographic primitive named threshold key-insulated signature(TKIS) and proposes a concrete TKIS *** a TKIS system,at least k out of n helpers are needed to update a user's temporary private *** the one hand,even if up to k 1 helpers are compromised in addition to the exposure of any of temporary private keys,security of the non-exposed periods is still *** the other hand,even if all the n helpers are compromised,we can still ensure the security of all periods as long as none of temporary private keys is *** with traditional key-insulated signature(KIS) schemes,the proposed TKIS scheme not only greatly enhances the security of the system,but also provides flexibility and efficiency.

关键词： threshold key-insulation signature random oracle model

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Exploiting idle register classes for fast spill destination

Exploiting idle register classes for fast spill destination

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22nd ACM International Conference on Supercomputing, ICS'08

作者： Lu, Fang Wang, Lei Feng, Xiaobing Li, Zhiyuan Zhang, Zhaoqing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100191 China Department of Computer Sciences Purdue University West Lafayette IN 47906 United States

ISBN: (纸本)9781605581583

On today's microprocessors, there often exist several different types of registers, e.g. general purpose registers and floating point registers. A given program may use one type of registers much more frequently than other types. This creates an opportunity to employ the infrequently used registers as spill destinations for the more frequently used register types. In this paper, we present a code optimization method named idle register exploitation (IRE) to exploit such opportunities. We developed a model, called the IRE model, or IREM, to determine the static performance gains of IRE versus spilling to the stack. On a microprocessor with fast data paths between different types of registers, we find that IRE method speeds up the execution of the SPECint benchmark suite from 1.7% to 10%. In contrast, on microprocessors with less efficient data transfer paths, the performance gain is limited. In some cases, performance may even suffer degradation. This result argues strongly for the adoption of fast data paths between different types of registers for the purpose of reducing register spills, which is important in view of the increased significance of memory bottlenecks on future microprocessors. Copyright 2008 ACM.

关键词： Data transfer

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Extendable pattern-oriented optimization directives

Extendable pattern-oriented optimization directives

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作者： Cui, Huimin Xue, Jingling Wang, Lei Yang, Yang Feng, Xiaobing Fan, Dongrui Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Beijing China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

Algorithm-specific, that is, semantic-specific optimizations have been observed to bring significant performance gains, especially for a diverse set of multi/many-core architectures. However, current programming models and compiler technologies for the state-of-the-art architectures do not exploit well these performance opportunities. In this article, we propose a pattern-making methodology that enables algorithm-specific optimizations to be encapsulated into "optimization patterns". Such optimization patterns are expressed in terms of preprocessor directives so that simple annotations can result in significant performance improvements. To validate this new methodology, a framework, named EPOD, is developed to map these directives into the underlying optimization schemes for a particular architecture. It is difficult to create an exact performance model to determine an optimal or near-optimal optimization scheme (including which optimizations to apply and in which order) for a specific application, due to the complexity of applications and architectures. However, it is trackable to build individual optimization components and let compiler developers synthesize an optimization scheme from these components. Therefore, our EPOD framework provides an Optimization Programming Interface (OPI) for compiler developers to define new optimization schemes. Thus, new patterns can be integrated into EPOD in a flexible manner. We have identified and implemented a number of optimization patterns for three representative computer platforms. Our experimental results show that a pattern-guided compiler can outperform the state-of-theart compilers and even achieve performance as competitive as hand-tuned code. Therefore, such a patternmaking methodology represents an encouraging direction for domain experts' experience and knowledge to be integrated into general-purpose compilers. © 2012 ACM.

关键词： Semantics

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Data protection and provenance in cloud of things environment: Research challenges

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International Journal of Information and computer Security 2020年第4期12卷 416-435页

作者： Wang, Chundong Yang, Lei Guo, Hao Wan, Fujin Key Laboratory of Computer Vision and System Tianjin Key Laboratory of Intelligence Computing and Novel Software Technology Ministry of Education Tianjin University of Technology Tianjin China Global Energy Internet Research Institute Beijing University of Technology Tianjin China Department of College of Computer and Control Engineering Nankai University Tianjin China

Internet of things are increasingly being deployed over the cloud (also referred to as cloud of things) to provide a broader range of services. However, there are serious challenges of CoT in the data protection and security provenance. This paper proposes a data privacy protection and provenance model (DPSPM) based on CoT. It can protect the privacy data of the users and trace the source of leaked data. In detail, security encryption and watermarking algorithms are proposed. Meanwhile, we use the improved k-anonymity data masking algorithm and pseudo-row watermarking algorithm in this scheme. Those algorithms can carry out security control over the whole process of data publishing, especially in data encryption, data masking and provenance verification. Finally, the experimental results show that our scheme has good efficiency. It is proved that the data masking time is proportional to the parameters k and L, the results also show good robustness to the common database watermarking attacks. © 2020 Inderscience Enterprises Ltd.

关键词： Data privacy

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Deceptive answer prediction with user preference graph

Deceptive answer prediction with user preference graph

引用

51st Annual Meeting of the Association for Computational Linguistics, ACL 2013

作者： Li, Fangtao Gao, Yang Zhou, Shuchang Si, Xiance Dai, Decheng Google Research Mountain View Institute of Computing Technology CAS China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS China Department of Computer Science and Technology Tsinghua University China

ISBN: (纸本)9781937284503

In Community question answering (QA) sites, malicious users may provide deceptive answers to promote their products or services. It is important to identify and filter out these deceptive answers. In this paper, we first solve this problem with the traditional supervised learning methods. Two kinds of features, including textual and contextual features, are investigated for this task. We further propose to exploit the user relationships to identify the deceptive answers, based on the hypothesis that similar users will have similar behaviors to post deceptive or authentic answers. To measure the user similarity, we propose a new user preference graph based on the answer preference expressed by users, such as "helpful" voting and "best answer" selection. The user preference graph is incorporated into traditional supervised learning framework with the graph regularization technique. The experiment results demonstrate that the user preference graph can indeed help improve the performance of deceptive answer prediction. © 2013 Association for Computational Linguistics.

关键词： Supervised learning

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Memory bandwidth optimization of SpMV on GPGPUs

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Frontiers of computer Science 2015年第3期9卷 431-441页

作者： Chenggang Clarence YAN Hui YU Weizhi XU Yingping ZHANG Bochuan CHEN Zhu TIAN Yuxuan WANG Jian YIN Key Lab of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Microelectronics Tsinghua University Beijing 100084 China Automation Department Tsinghua University Beijing 100084 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China State Grid Information & Communication Company of Hunan EPC Changsha 410007 China Department of Computer Shandong University Weihai 250101 China

It is an important task to improve performance for sparse matrix vector multiplication （SpMV）, and it is a difficult task because of its irregular memory access. Gen- eral purpose GPU （GPGPU） provides high computing abil- ity and substantial bandwidth that cannot be fully exploited by SpMV due to its irregularity. In this paper, we propose two novel methods to optimize the memory bandwidth for SpMV on GPGPU. First, a new storage format is proposed to exploit memory bandwidth of GPU architecture more effi- ciently. The new storage format can ensure that there are as many non-zeros as possible in the format which is suitable to exploit the memory bandwidth of the GPU. Second, we pro- pose a cache blocking method to improve the performance of SpMV on GPU architecture. The sparse matrix is partitioned into sub-blocks that are stored in CSR format. With the block- ing method, the corresponding part of vector x can be reused in the GPU cache, so the time to access the global memory for vector x is reduced heavily. Experiments are carried out on three GPU platforms, GeForce 9800 GX2, GeForce GTX 480, and Tesla K40. Experimental results show that both new methods can efficiently improve the utilization of GPU mem- ory bandwidth and the performance of the GPU.

关键词： GPGPU performance tuning SpMV cacheblocking memory bandwidth

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Reducing Synchronization Cost for Single-Level Store in Mobile systems

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Journal of computer Science & technology 2016年第4期31卷 836-848页

作者： Yuan-Chao Xu Hu Wan Ke-Ni Qiu Tao Li Wei-Gong Zhang College of Information Engineering Capital Normal University Beijing 100048 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Electrical and Computer Engineering University of Florida Gainesville FL 32611 U.S.A.

Emerging byte-addressable non-volatile memory technologies, such as phase change memory （PCM） and spin- transfer torque RAM （STT-RAM）, offer both the byte-addressability of memory and the durability of storage, thus making it feasible to build single-level store systems. To ensure the consistency of persistent data structures in the presence of power failures or system crashes, it requires flushing cache lines to persistent memory frequently, thus incurring non-trivial synchronization overhead. To mitigate this issue, we propose two techniques. First, we use non-volatile STT-RAM as scratchpad memory on chip to store recovery information, thereby eliminating synchronization cost in the logging phase due to the avoidance of off-chip logging operations. Second, we present an adaptive synchronization policy based on caching modes in terms of data access patterns, thereby eliminating unnecessary synchronization cost in the checkpoint phase. Evaluation results indicate that the two techniques improve the overall performance from 2.15x to 2.39x compared with conventional transactional persistent memory.

关键词： crash consistency synchronization cost persistent memory power failure mobile system

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An efficient and flexible task management for many cores

An efficient and flexible task management for many cores

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作者： Yuan, Nan Yu, Lei Fan, Dong-Rui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9783642245671

This paper presents the design and implementation of a runtime system (named "GodRunner") on Godson-T many-core processor to support task-level parallelism efficiently and flexibly. GodRunner abstracts underlying hardware resource, providing ease-of-use programming interface. A two-grade task management mechanism is proposed to support both coarse-grained and fine-grained multithreading efficiently. Two load-balanced scheduling policies are combined flexibly in GodRunner. The software-controlled task management makes GodRunner more configurable and extensible than hard-wired ones. The experiment shows that the tasking overhead in GodRunner is as small as hundreds of cycles, which is about the hundreds of times faster than the conventional Pthread based multithreading on a SMP machine. Furthermore, our approach scales well and supports fine-grained tasks as small as 20k cycles optimally. © 2011 Springer-Verlag Berlin Heidelberg.

关键词： computer architecture

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