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检索条件"机构=Key Laboratory of Computer System and Architecture Institute of Computing Technology"
1012 条 记 录,以下是201-210 订阅
排序:
Tetris:A Heuristic Static Memory Management Framework for Uniform Memory Multicore Neural Network Accelerators
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Journal of computer Science & technology 2022年 第6期37卷 1255-1270页
作者: Xiao-Bing Chen Hao Qi Shao-Hui Peng Yi-Min Zhuang Tian Zhi Yun-Ji Chen Distinguished Member,CCF State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China University of Chinese Academy of Sciences Beijing 100049China School of Computer Science and Technology University of Science and Technology of ChinaHeFei230026China Chinese Academy of Sciences Center for Excellence in Brain Science and Intelligence Technology Shanghai200031China 不详
Uniform memory multicore neural network accelerators(UNNAs)furnish huge computing power to emerging neural network ***,with neural network architectures going deeper and wider,the limited memory capacity has become a ... 详细信息
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A Pipelining Loop Optimization Method for Dataflow architecture
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Journal of computer Science & technology 2018年 第1期33卷 116-130页
作者: Xu Tan Xiao-Chun Ye Xiao-Wei Shen Yuan-Chao Xu Da Wang Lunkai Zhang Wen-Ming Li Dong-Rui Fan Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 1000J9 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125 China College of Information Engineering Capital Normal University Beijing 100048 China Department of Computer Science The University of Chicago Chicago IL 60637 U.S.A.
With the coming of exascale supercomputing era, power efficiency has become the most important obstacle to build an exascale system. Dataflow architecture has native advantage in achieving high power efficiency for sc... 详细信息
来源: 评论
The rise of high-throughput computing
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Frontiers of Information technology & Electronic Engineering 2018年 第10期19卷 1245-1250页
作者: Ning-hui SUN Yun-gang BAO Dong-rui FAN State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesUniversity of Chinese Academy of Sciences
In recent years, the advent of emerging computing applications, such as cloud computing, artificial intelligence, and the Internet of Things, has led to three common requirements in computer system design: high utili... 详细信息
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piRT-IFC:Physics-informed real-time impedance flow cytometry for the characterization of cellular intrinsic electrical properties
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Microsystems & Nanoengineering 2023年 第3期9卷 347-356页
作者: Xiaofeng Luan Pengbin Liu Di Huang Haiping Zhao Yuang Li Sheng Sun Wenchang Zhang Lingqian Zhang Mingxiao Li Tian Zhi Yang Zhao Chengjun Huang Institute of Microelectronics of the Chinese Academy of Sciences BeijingChina University of Chinese Academy of Sciences BeijingChina State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijingChina Cerebrovascular Diseases Research Institute Xuanwu Hospital of Capital Medical UniversityBeijingChina
Real-time transformation was important for the practical implementation of impedance flow *** major obstacle was the time-consuming step of translating raw data to cellular intrinsic electrical properties(e.g.,specifi... 详细信息
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Poster: Revisiting virtual channel memory for performance and fairness on multi-core architecture  11
Poster: Revisiting virtual channel memory for performance an...
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Proceedings of the international conference on Supercomputing
作者: Chen, Licheng Huang, Yongbing Bao, Yungang Mutlu, Onur Tan, Guangming Chen, Mingyu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School of Chinese Academy of Sciences China Carnegie Mellon University United States
In modern multi-core chip architecture, the DRAM system is shared by more and more cores and high bandwidth I/O devices. This trend would make the problem of request contention and un-fairness more serious. Previous r... 详细信息
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Adapting Memory Hierarchies for Emerging Datacenter Interconnects
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Journal of computer Science & technology 2015年 第1期30卷 97-109页
作者: 江涛 侯锐 董建波 柴琳 Sally A. McKee 田斌 张立新 孙凝晖 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China Computer Science and Engineering Chalmers University of Technology Gothenburg 41296 Sweden National High Performance Integrated Circuit Design Center (Shanghai) Shanghai 201204 China
Efficient resource utilization requires that emerging datacenter interconnects support both high performance communication and efficient remote resource sharing. These goals require that the network be more tightly co... 详细信息
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Extended selective encoding of scan slices for reducing test data and test power
Extended selective encoding of scan slices for reducing test...
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18th Asian Test Symposium, ATS 2009
作者: Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Information Hefei University of Technology Hefei China Academy of Sciences Graduate University of Chinese Beijing China
Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying sing... 详细信息
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Accelerate Bit Manipulation in XiangShan Processer Using RISC-V B Extension and Instruction Fusion
Accelerate Bit Manipulation in XiangShan Processer Using RIS...
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2022 International Conference on Cloud computing, Internet of Things, and computer Applications, CICA 2022
作者: Zhang, Fawang Tang, Dan Cai, Ye College of Computer Science and Software Engineering Shenzhen University Shenzhen China State Key Laboratory of Computer Architecture Institute of Computing Technology Beijing China
In the field of high-performance computing, some application scenarios make extensive use of bit manipulation. RISC-V foundation issues B extension to reduce the number of instructions during the static compilation. B... 详细信息
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Eliminating data invalidation in debugging multiple-clock chips
Eliminating data invalidation in debugging multiple-clock ch...
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作者: Gao, Jianliang Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Information Science and Engineering Central South University China
A critical concern for post-silicon debug is the need to control the chip at clock cycle level. In a single clock chip, run-stop control can be implemented by gating the clock signal using a stop signal. However, data... 详细信息
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TSCMR:Two-Stage Cross-Modal Retrieval  9th
TSCMR:Two-Stage Cross-Modal Retrieval
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19th International Conference on Advanced Data Mining and Applications, ADMA 2023
作者: Chen, Zhihao Wang, Hongya School of Computer Science and Technology Donghua University Shanghai China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China Shanghai Key Laboratory of Computer Software Evaluating and Testing Shanghai China
Currently, large-scale vision and language models has significantly improved the performances of cross-modal retrieval tasks. However, large-scale models require a substantial amount of computing resources, so the exe... 详细信息
来源: 评论