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Fast and efficient parallel breadth-first search with power-law graph transformation

Frontiers of computer Science 2022年第5期16卷 225-227页

作者： Zite JIANG Tao LIU Shuai ZHANG Mengting YUAN Haihang YOU School of Computer Science and Technology University of Chinese Academy of SciencesBeijing 100049China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Comptuer Science Wuhan UniversityWuhan 430072China

1 Introduction Most real-world graphs are large-scale but unstructured and *** of the most notable characteristics of real-world graphs is the skewed power law degree distribution[1]:most vertices have a few neighbors while a few own a large number of *** characteristics present challenges for efficient parallel graph processing,such as load imbalance,poor locality,and redundant *** from modifying the graph programming abstraction or changing the execution models on different architectures,reducing the irregularity of graph data also improves the performance of graph processing[2].For example,it is wellknown that BFS has a bad temporal locality,but it is possible to transform irregular graphs to more regular ones to improve spatial locality and gain more performance.

关键词： neighbor programming redundant

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BTBench: A Benchmark for Comprehensive Binary Translation Performance Evaluation

BTBench: A Benchmark for Comprehensive Binary Translation Pe...

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2024 IEEE International Symposium on Performance Analysis of systems and Software, ISPASS 2024

作者： Li, Xinyu Lan, Yanzhi Niu, Gen Xue, Feng Zhang, Fuxin Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences State Key Laboratory of Computer Architecture China

ISBN: (纸本)9798350376388

Binary translation serves as a fundamental technol-ogy for instruction set emulation, system virtualization, runtime instrumentation, and numerous other applications. Many techniques have been proposed to enhance the efficiency of binary translation systems. However, imprecise performance evaluation leads to potential performance shortcomings of binary translators in real-world applications. Previous studies primarily employ CPU benchmarks, which may overlook performance issues spe-cific to binary translators and fail to guide for optimizing binary translation. To address this issue, we propose a new benchmark suite named BTBench(Binary Translation Benchmark), which provides a convenient, portable, and comprehensive solution. BT-Bench takes into account the inherent attributes of binary trans-lators, such as translation and code-cache lookup overhead. We carefully select benchmarks that offer comprehensive coverage and align with real-world application scenarios. To validate the effectiveness of BTBench, we conducted rigorous experimentation on four widely-used binary translators. The analysis of the results reveals that, compared to existing CPU benchmarks, BTBench is better suited for identifying potential performance shortcomings, providing invaluable insights for future optimization efforts. The BTBench benchmark suite is publicly available 1 • © 2024 IEEE.

关键词： Benchmarking

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Chameleon: A data organization transformation scheme for big data systems 14

Chameleon: A data organization transformation scheme for big...

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11th ACM International Conference on computing Frontiers, CF 2014

作者： Pan, Fengfeng Yue, Yinliang Xiong, Jin State Key Laboratory of Computer Architecture Institute of Computing Technology CAS China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450328708

Big data system requires multiple types of data organi-zations to effciently support various operations. It is well known that in-place update index, unordered log structured index and ordered log structured index are three typical data organizations which are designed to meet different workload requirements respectively. Differentiated workload requirements in different phase of the data life-cycle lead to data organization transformation. However, typical sequential data organization transformation not only incurs extremely long time, but also signicant energy consumption. In this paper, we propose Chameleon, a novel data organization transformation scheme for replication based big data system. The goal of Chameleon is to signi-cantly shorten the data organization transformation process and improve the write performance and the subsequent read performance through data organization transformation, meanwhile eliminate the additional hardware and energy costs by reusing the mirrored disks. For each put request, Chameleon keeps two copies of the key-value pair. One in its normal place and organized in ordered log structured index, and the other in relatively high performance log disk and organized in unordered log structured index. By spreading destaging I/O activities among short idle time slots, key-value pairs are transformed from write-optimized index to read-optimized index. Extensive experimental evaluation based on our prototype shows that Chameleon can shorten the time of data organization transformation and enhance energy effciency and performance. © is held by the owner/authors.

关键词： Big data

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Tetris:A Heuristic Static Memory Management Framework for Uniform Memory Multicore Neural Network Accelerators

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Journal of computer Science & technology 2022年第6期37卷 1255-1270页

作者： Xiao-Bing Chen Hao Qi Shao-Hui Peng Yi-Min Zhuang Tian Zhi Yun-Ji Chen Distinguished Member,CCF State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China University of Chinese Academy of Sciences Beijing 100049China School of Computer Science and Technology University of Science and Technology of ChinaHeFei230026China Chinese Academy of Sciences Center for Excellence in Brain Science and Intelligence Technology Shanghai200031China 不详

Uniform memory multicore neural network accelerators(UNNAs)furnish huge computing power to emerging neural network ***,with neural network architectures going deeper and wider,the limited memory capacity has become a constraint to deploy models on UNNA *** how to efficiently manage memory space and how to reduce workload footprints are urgently *** this paper,we propose Tetris:a heuristic static memory management framework for UNNA *** reconstructs execution flows and synchronization relationships among cores to analyze each tensor’s liveness *** the memory management problem is converted to a sequence permutation *** uses a genetic algorithm to explore the permutation space to optimize the memory management strategy and reduce memory *** evaluate several typical neural networks and the experimental results demonstrate that Tetris outperforms the state-of-the-art memory allocation methods,and achieves an average memory reduction ratio of 91.9%and 87.9%for a quad-core and a 16-core Cambricon-X platform,respectively.

关键词： multicore neural network accelerators liveness analysis static memory management memory reuse genetic algorithm

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A Pipelining Loop Optimization Method for Dataflow architecture

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Journal of computer Science & technology 2018年第1期33卷 116-130页

作者： Xu Tan Xiao-Chun Ye Xiao-Wei Shen Yuan-Chao Xu Da Wang Lunkai Zhang Wen-Ming Li Dong-Rui Fan Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 1000J9 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125 China College of Information Engineering Capital Normal University Beijing 100048 China Department of Computer Science The University of Chicago Chicago IL 60637 U.S.A.

With the coming of exascale supercomputing era, power efficiency has become the most important obstacle to build an exascale system. Dataflow architecture has native advantage in achieving high power efficiency for scientific applications. However, the state-of-the-art dataflow architectures fail to exploit high parallelism for loop processing. To address this issue, we propose a pipelining loop optimization method （PLO）, which makes iterations in loops flow in the processing element （PE） array of dataflow accelerator. This method consists of two techniques, architecture-assisted hardware iteration and instruction-assisted software iteration. In hardware iteration execution model, an on-chip loop controller is designed to generate loop indexes, reducing the complexity of computing kernel and laying a good f（mndation for pipelining execution. In software iteration execution model, additional loop instructions are presented to solve the iteration dependency problem. Via these two techniques, the average number of instructions ready to execute per cycle is increased to keep floating-point unit busy. Simulation results show that our proposed method outperforms static and dynamic loop execution model in floating-point efficiency by 2.45x and 1.1x on average, respectively, while the hardware cost of these two techniques is acceptable.

关键词： dataflow model control-flow model loop optimization exascale computing scientific application

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The rise of high-throughput computing

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Frontiers of Information technology & Electronic Engineering 2018年第10期19卷 1245-1250页

作者： Ning-hui SUN Yun-gang BAO Dong-rui FAN State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesUniversity of Chinese Academy of Sciences

In recent years, the advent of emerging computing applications, such as cloud computing, artificial intelligence, and the Internet of Things, has led to three common requirements in computer system design： high utilization, high throughput, and low latency. Herein, these are referred to as the requirements of ＇high-throughput computing （HTC）＇. We further propose a new indicator called ＇sysentropy＇ for measuring the degree of chaos and uncertainty within a computer system. We argue that unlike the designs of traditional computing systems that pursue high performance and low power consumption, HTC should aim at achieving low sysentropy. However, from the perspective of computer architecture, HTC faces two major challenges that relate to （1） the full exploitation of the application＇s data parallelism and execution concurrency to achieve high throughput, and （2） the achievement of low latency, even in the cases at which severe contention occurs in data paths with high utilization. To overcome these two challenges, we introduce two techniques： on-chip data flow architecture and labeled von Neumann architecture. We build two prototypes that can achieve high throughput and low latency, thereby significantly reducing sysentropy.

关键词： High-throughput computing Sysentropy Information superbahn

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piRT-IFC:Physics-informed real-time impedance flow cytometry for the characterization of cellular intrinsic electrical properties

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Microsystems & Nanoengineering 2023年第3期9卷 347-356页

作者： Xiaofeng Luan Pengbin Liu Di Huang Haiping Zhao Yuang Li Sheng Sun Wenchang Zhang Lingqian Zhang Mingxiao Li Tian Zhi Yang Zhao Chengjun Huang Institute of Microelectronics of the Chinese Academy of Sciences BeijingChina University of Chinese Academy of Sciences BeijingChina State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijingChina Cerebrovascular Diseases Research Institute Xuanwu Hospital of Capital Medical UniversityBeijingChina

Real-time transformation was important for the practical implementation of impedance flow *** major obstacle was the time-consuming step of translating raw data to cellular intrinsic electrical properties(e.g.,specific membrane capacitance C_(sm) and cytoplasm conductivityσ_(cyto)).Although optimization strategies such as neural network-aided strategies were recently reported to provide an impressive boost to the translation process,simultaneously achieving high speed,accuracy,and generalization capability is still *** this end,we proposed a fast parallel physical fitting solver that could characterize single cells’C_(sm)andσ_(cyto)within 0.62 ms/cell without any data preacquisition or pretraining *** achieved the 27000-fold acceleration without loss of accuracy compared with the traditional *** on the solver,we implemented physics-informed real-time impedance flow cytometry(piRT-IFC),which was able to characterize up to 100,902 cells’C_(sm) andσ_(cyto)within 50 min in a real-time *** to the fully connected neural network(FCNN)predictor,the proposed real-time solver showed comparable processing speed but higher ***,we used a neutrophil degranulation cell model to represent tasks to test unfamiliar samples without data for *** being treated with cytochalasin B and N-Formyl-Met-Leu-Phe,HL-60 cells underwent dynamic degranulation processes,and we characterized cell’s C_(sm)andσ_(cyto)using *** to the results from our solver,accuracy loss was observed in the results predicted by the FCNN,revealing the advantages of high speed,accuracy,and generalizability of the proposed piRT-IFC.

关键词： impedance intrinsic flow

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Poster: Revisiting virtual channel memory for performance and fairness on multi-core architecture 11

Poster: Revisiting virtual channel memory for performance an...

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Proceedings of the international conference on Supercomputing

作者： Chen, Licheng Huang, Yongbing Bao, Yungang Mutlu, Onur Tan, Guangming Chen, Mingyu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School of Chinese Academy of Sciences China Carnegie Mellon University United States

ISBN: (纸本)9781450301022

In modern multi-core chip architecture, the DRAM system is shared by more and more cores and high bandwidth I/O devices. This trend would make the problem of request contention and un-fairness more serious. Previous research focused on memory sche-duling mechanisms to efficiently and fairly serve memory requests generated by multiple cores. However, the performance is mod-erately improved due to the limited bank-level parallelism in preva-lent DRAM chips. Based on the observation that virtual channel memory (VCM) provides more opportunities for exploiting MLP because it has more channel buffers than banks in conventional DRAM chip, we evaluate VCM technology as an alternative to DRAM for addressing the issues of contention, unfairness and MLP. In this work we implement VCM and leverage the state of art scheduling mechanism on a multi-core architecture. The experi-mental results show that (i) VCM with 32 channels improves ho-mogeneous workloads' IPC by 2.08X on a 16-core system compared to the system with conventional DRAM chips, causing extra area cost by 0.5%, and dynamic and background power pe-nalties by only 5.8% and 0.03% respectively. (ii) For heterogene-ous workloads, VCM significantly reduces unfairness by 82.0% as well as improves the workloads' performance by 1.86X in term of system throughput. © 2011 Authors.

关键词： Dynamic random access storage

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Adapting Memory Hierarchies for Emerging Datacenter Interconnects

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Journal of computer Science & technology 2015年第1期30卷 97-109页

作者：江涛侯锐董建波柴琳 Sally A. McKee 田斌张立新孙凝晖 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China Computer Science and Engineering Chalmers University of Technology Gothenburg 41296 Sweden National High Performance Integrated Circuit Design Center (Shanghai) Shanghai 201204 China

Efficient resource utilization requires that emerging datacenter interconnects support both high performance communication and efficient remote resource sharing. These goals require that the network be more tightly coupled with the CPU chips. Designing a new interconnection technology thus requires considering not only the interconnection itself, but also the design of the processors that will rely on it. In this paper, we study memory hierarchy implications for the design of high-speed datacenter interconnects particularly as they affect remote memory access -- and we use PCIe as the vehicle for our investigations. To that end, we build three complementary platforms： a PCIe-interconnected prototype server with which we measure and analyze current bottlenecks; a software simulator that lets us model microarchitectural and cache hierarchy changes; and an FPGA prototype system with a streamlined switchless customized protocol Thunder with which we study hardware optimizations outside the processor. We highlight several architectural modifications to better support remote memory access and communication, and quantify their impact and ]imitations.

关键词： high-speed interconnect memory hierarchy time shared memory datacenter network

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Extended selective encoding of scan slices for reducing test data and test power

Extended selective encoding of scan slices for reducing test...

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18th Asian Test Symposium, ATS 2009

作者： Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Information Hefei University of Technology Hefei China Academy of Sciences Graduate University of Chinese Beijing China

ISBN: (纸本)9780769538648

Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding. © 2009 IEEE.

关键词： Filling

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