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Eliminating data invalidation in debugging multiple-clock chips

Eliminating data invalidation in debugging multiple-clock ch...

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作者： Gao, Jianliang Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Information Science and Engineering Central South University China

ISBN: (纸本)9783981080179

A critical concern for post-silicon debug is the need to control the chip at clock cycle level. In a single clock chip, run-stop control can be implemented by gating the clock signal using a stop signal. However, data invalidation might occur when it comes to multiple-clock chips. In this paper, we analyze the possible data invalidation, including data repetition and data loss, when stopping and resuming a multiple-clock chip. Furthermore, we propose an efficient solution to eliminate data repetition and data loss. Theoretical analysis and simulation experiments are both conducted for the proposed solution. We implement the proposed Design-for-Debug (DfD) circuit with SMIC 0.18/Ltm technology and simulate the data transfer across clock domains using SPICE tool. The results show that both data repetition and data loss can be avoided with the proposed solution, even if metastability occurs. © 2011 EDAA.

关键词： Clocks

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TSCMR:Two-Stage Cross-Modal Retrieval 9th

TSCMR:Two-Stage Cross-Modal Retrieval

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19th International Conference on Advanced Data Mining and Applications, ADMA 2023

作者： Chen, Zhihao Wang, Hongya School of Computer Science and Technology Donghua University Shanghai China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China Shanghai Key Laboratory of Computer Software Evaluating and Testing Shanghai China

ISBN: (纸本)9783031466731

Currently, large-scale vision and language models has significantly improved the performances of cross-modal retrieval tasks. However, large-scale models require a substantial amount of computing resources, so the execution of these models on devices with limited resources is challenging. Thus, it is paramount to reduce the model size and minimize computing costs of a model without sacrificing its performance. In this paper, we improved TERAN by dividing cross-modal retrieval into two stages: image-text coarse-grained matching and image-text fine-grained matching. Specifically, we present a novel approach called Two-Stage Cross-Modal Retrieval network(TSCMR). To reduce model size after model training, our approach utilized a new knowledge distillation method for Transformer-based models. Experiments have shown that our approach maintains a performance comparable to TERAN on the MS-COCO 1K test set, while being 2x smaller and 3.1x faster on inference. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Distillation

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Accelerate Bit Manipulation in XiangShan Processer Using RISC-V B Extension and Instruction Fusion

Accelerate Bit Manipulation in XiangShan Processer Using RIS...

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2022 International Conference on Cloud computing, Internet of Things, and computer Applications, CICA 2022

作者： Zhang, Fawang Tang, Dan Cai, Ye College of Computer Science and Software Engineering Shenzhen University Shenzhen China State Key Laboratory of Computer Architecture Institute of Computing Technology Beijing China

ISBN: (纸本)9781510656673

In the field of high-performance computing, some application scenarios make extensive use of bit manipulation. RISC-V foundation issues B extension to reduce the number of instructions during the static compilation. But this extension does not cover the more frequent operations fully. Instruction fusion technology can fuse multiple instructions into one instruction at the decode stage to dynamically reduce the number of instructions. Therefore, this technology can supplement RISC-V B extension uncovered instruction, enhancing the processor’s capabilities for bit manipulation. This paper implements the RISC-V B extension 1.0 version on the Xiangshan processor. For accelerating more bit manipulation, we profiled general benchmarks by the simulator, proposed ten new instructions fusion targets, and implemented a fusion decode unit. Finally, we use Coremark and SPEC CPU 2006 integer to evaluate the performance. The Coremark results show that dynamic instructions reduce by 18.14%, and the performance improves by 12.09%. © 2022 SPIE.

关键词： Decoding

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Modeling the failures of power-aware data centers by leveraging heat recirculation

Modeling the failures of power-aware data centers by leverag...

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作者： Feng, Hao Deng, Yuhui Yu, Liang Department of Computer Science Jinan University Guangzhou China Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

With the explosive growth of data, hundreds of thousands of servers may be contained in a single data center. Hence, node failures are unavoidable and generally negatively effects the performance of the whole data center. Additionally, data centers with a large number of nodes will cause plenty of energy consumption. Many existing task scheduling techniques can effectively reduce the power consumption in data centers by considering heat recirculation. However, the traditional techniques do not take the situation of node failures into account. This paper proposes an airflow-based failure model for data centers by leveraging heat recirculation. In this model, the spatial distribution and time distribution of failures are considered. Furthermore, a genetic algorithm (GA) and a simulated annealing algorithm (SA) are implemented to evaluate the proposed failure model. Because the positions of node failures have a significant impact on the heat recirculation and the energy consumption of data centers, failures with different positions are analyzed and evaluated. The experimental results demonstrate that the energy consumption of data centers can be significantly reduced by using the GA and SA algorithms for task scheduling based on the proposed failure model. © 2019 John Wiley & Sons, Ltd.

关键词： Energy efficiency

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Energy-Efficient and Reliable Federated Learning in Heterogeneous Mobile-Edge computing 19

Energy-Efficient and Reliable Federated Learning in Heteroge...

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2022 IEEE SmartWorld, 19th IEEE International Conference on Ubiquitous Intelligence and computing, 2022 IEEE International Conference on Autonomous and Trusted Vehicles Conference, 22nd IEEE International Conference on Scalable computing and Communications, 2022 IEEE International Conference on Digital Twin, 8th IEEE International Conference on Privacy computing and 2022 IEEE International Conference on Metaverse, SmartWorld/UIC/ATC/ScalCom/DigitalTwin/PriComp/Metaverse 2022

作者： Xu, Yan Li, Liying Cong, Peijin Zhou, Junlong Nanjing University of Science and Technology School of Computer Science and Engineering China Institute of Computing Technology Chinese Academy of Sciences State Key Laboratory of Computer Architecture China

ISBN: (纸本)9798350346558

As a decentralized machine learning paradigm, Federated Learning (FL) is an emerging technique to protect user data privacy in Mobile Edge computing (MEC). FL adopts the idea of distributed privacy computing, enabling the terminal devices to train machine learning models required by servers locally and upload model parameters to servers for aggregation. However, in the process of coupling FL with MEC systems, device heterogeneity, malicious use of poisoned data by users and limited system resources will seriously affect FL training accuracy, system reliability and energy efficiency. In this paper, a highly reliable and energy-efficient FL scheme is designed to solve these issues. Specifically, we first propose a calculation method for estimating the reliability of heterogeneous devices. Then, we design a highly reliable device selection scheme based on devices' reliability, computing power, and participation times. Finally, we utilize the slack time in FL training to dynamically adjust the voltage and frequency of devices for reducing the energy consumption of training. Experimental results show that our proposed scheme improves the accuracy by up to 36.45% on average and saves energy by up to 48.63% when compared to the baseline and benchmarking methods. © 2022 IEEE.

关键词： Reliability

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Building Agile Workflow Microservice system for HPC Applications Based on Fast-start OSv 27

Building Agile Workflow Microservice System for HPC Applicat...

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27th IEEE International Conference on Parallel and Distributed systems, ICPADS 2021

作者： Hu, Qiang Ma, Lixian Shao, En Tan, Guangming Institute of Computing Technology CAS State Key Laboratory of Computer Architecture Beijing China University of Chinese Academy of Science Beijing China

ISBN: (纸本)9781665408783

The advances of containers have significantly promoted the development of microservice architecture. This architecture splits a monolithic application into multiple independent components and the container orchestrator manages these components by the container in the cloud environment. The feasibility of deploying high performance computing(HPC) applications as microservices has been proven, but the existing container orchestrator incurs a large performance overhead as there is interference between different containers on the same physical host. In this paper, we design an agile workflow microservice system for HPC applications with fast-start OSv. We consider improving HPC workflow performance from two aspects: single OSv startup time optimization and workflow orchestration optimization. For single OSv startup time optimization, we design a fast-start OSv by analyzing the process of OSv startup and finding an optimization by modifying OSv source code. In this way, we get nearly 50% improvement of startup time. For workflow orchestration optimization, we propose four optimization techniques to speed up the execution of workflow by jointly considering OSv and workflow features, namely: node fusion, node merge, image preload, boot delay. Furthermore, we utilize our fast startup OSv to design an orchestration system for efficiently building an agile HPC workflow microservice by Kubevirt. Our experimental results optimization microservice system reduces the execution time by 30% compared with the original deployment with docker. © 2021 IEEE.

关键词： Containers

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Protein structure superposition by curve moment invariants and iterative closest point

Protein structure superposition by curve moment invariants a...

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2007 1st International Conference on Bioinformatics and Biomedical Engineering, ICBBE

作者： Xu, Dong Li, Hua Gu, Tongjun Key Laboratory of Intelligent Information Processing Key Laboratory of Computer System and Architecture National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Center for Systems Biology Institute of Biophysics Chinese Academy of Sciences Graduate University Chinese Academy of Sciences

ISBN: (纸本)1424411203

Superimpose one protein tertiary structure to another can help to find similarity between them and further identify functional and evolutionary relationships. We first extract invariant features under rigid body transformation for each protein backbone which is represented by alpha-carbons of all the residues. Then, the invariant features are embedded with Iterative Closest Point algorithm for superposition. With several initialized orientations, pairwise alignment can be achieved accurately only by few iterations. Experiments indicate that our proposed algorithm is competitive with several well-known algorithms and with smallest root mean squared distance. © 2007 IEEE.

关键词： Proteins

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Poster: Revisiting linpack algorithm on large-scale CPU-GPU heterogeneous systems 25

Poster: Revisiting linpack algorithm on large-scale CPU-GPU ...

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25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2020

作者： Shui, Chaoyang Yu, Xianzhi Yan, Yujin Wang, Yinshan Meng, Ke Tan, Guangming State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9781450368186

As the widening gap between GPU computing capability and other components (CPU, PCIe bus and communication network), it’s increasingly challenging to design high performance parallel algorithms for large CPU-GPU heterogeneous systems. There are mainly two reasons. Firstly, simply offloading the kernel library to GPU incurs large volume data transfer through low-speed PCIe bus. Secondly, communication overheads through network severely affects scalability. To solve the above issues, we advocate a paradigm shift to GPU-centric and fine-grained pipelining algorithm design. By taking Linpack benchmark as a case study, the new algorithm design paradigm shows its effectiveness. Our optimized Linpack program achieves 63.79PFlops on 16384 GPUs. Its floating-point efficiency outperforms the NVIDIA proprietary counterparts by 5% on average. © 2020 Copyright held by the owner/author(s).

关键词： Graphics processing unit

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HMTT: A hybrid hardware/software tracing system for bridging the DRAM access trace's semantic gap

HMTT: A hybrid hardware/software tracing system for bridging...

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作者： Huang, Yongbing Chen, Licheng Cui, Zehan Ruan, Yuan Bao, Yungang Chen, Mingyu Sun, Ninghui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

DRAM access traces (i.e., off-chip memory references) can be extremely valuable for the design of memory subsystems and performance tuning of software. Hardware snooping on the off-chip memory interface is an effective and nonintrusive approach to monitoring and collecting real-life DRAM accesses. However, compared with software-based approaches, hardware snooping approaches typically lack semantic information, such as process/function/object identifiers, virtual addresses, and lock contexts, that is essential to the complete understanding of the systems and software under investigation. In this article, we propose a hybrid hardware/software mechanism that is able to collect off-chip memory reference traces with semantic information. We have designed and implemented a prototype system called HMTT (Hybrid Memory Trace Tool), which uses a custom-made DIMM connector to collect off-chip memory references and a high-level event-encoding scheme to correlate semantic information with memory references. In addition to providing complete, undistorted DRAM access traces, the proposed system is also able to perform various types of low-overhead profiling, such as object-relative accesses and multithread lock accesses. © 2014 ACM.

关键词： Dynamic random access storage

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Fault diagnosis of arbiter physical unclonable function 20

Fault diagnosis of arbiter physical unclonable function

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20th Design, Automation and Test in Europe, DATE 2017

作者： Ye, Jing Quo, Qingli Hu, Yu Li, Xiaowei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9783981537093

Physical Unclonable Function (PUF) has broad application prospects in the field of hardware security. If faults happen in PUF during manufacturing, the security of whole chip will be threatened. Fault diagnosis plays an important role in the yield learning process. However, since different manufactured PUFs with the same design have different Challenge-Response Pairs (CRPs), which cannot be predicted, the traditional fault diagnosis method based on comparing the fault-free responses of a design and the failing responses of chips is no longer suitable for diagnosing PUF. Therefore, this paper proposes a fault diagnosis method toward classic arbiter PUF. The stuck-at faults and the delay faults are considered. Based on the expected uniformity of arbiter PUF, a diagnostic challenge generation method and a corresponding CRP analysis method are proposed to distinguish faults within the arbiter PUF. Experimental results show that the diagnostic accuracy achieves 100.0% with good diagnostic resolution. © 2017 IEEE.

关键词： Failure analysis

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