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21st IEEE International Conference on High Performance computing and Communications, 17th IEEE International Conference on Smart City and 5th IEEE International Conference on Data Science and systems, HPCC/SmartCity/DSS 2019

作者： Shao, En Tan, Guangming Wang, Zhan Sun, Ninghui State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781728120584

During the improved process of hardware technology and program optimization in the high-performance computer (HPC), the overall computing ability of supercomputer increases correspondingly. As a large-scale system and a milestone to the HPC community shortly, the envisioned exascale computer will be comprised of nearly 5000 interconnected nodes and tens of thousands of computing nodes. Interconnection innovations in such a system are critical to improving overall computing ability. In this paper, we investigate optoelectronic interconnection in an exascale computer system design. Here, we propose a new software stack called Optoelectronic Interconnection Middleware (OeIM) to enable efficient utilization of the optical interconnection. OeIM allows for the use of two novel functions, namely the reconfigurable function and the running-time function. We evaluate OeIM using both communication benchmark (IMB) and real-world motif applications (Linpack, HPCG, and Graph500) in a prototyped exascale computer. The experiment shows that OeIM reduced latency by form 20 to 35% in the large-range communication, improved throughput by 30% in the long-distance communication, and improved the motif applications by more than 10%. Together, our results demonstrate that OeIM is an effective bridge between the optical switching device and system scheduler to improve communication capability. © 2019 IEEE.

关键词： Middleware

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Deep Reinforcement Agent for Failure-aware Job scheduling in High-Performance computing 27

Deep Reinforcement Agent for Failure-aware Job scheduling in...

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27th IEEE International Conference on Parallel and Distributed systems, ICPADS 2021

作者： Yang, Kang Cao, Rongyu Zhou, Yueyuan Zhang, Jiawei Shao, En Tan, Guangming Institute of Computing Technology CAS State Key Laboratory of Computer Architecture Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665408783

Job scheduling is crucial in high-performance computing (HPC), which is dedicated to deciding when and which jobs are allocated to the system and placing the jobs on which resources, by considering multiple scheduling goals. Along with the incremental of various resources and dazzling deep learning training (DLT) workloads, job failure becomes a quite common issue in HPC, which will affect user satisfaction and cluster utilization. To alleviate the influence of hardware and software errors as much as possible, in this paper, we aim to tackle the problem of failure-aware job scheduling in HPC clusters. Inspired by the success of previous studies of deep reinforcement learning-driven job scheduling, we propose a novel HPC scheduling agent named FARS (Failure-aware RL-based scheduler) by considering the effects of job failures. On the one hand, a neural network is applied to map the information of raw cluster and job states to job placement decisions. On the other hand, to consider the influence of job failure for user satisfaction and cluster utilization, FARS leverages make-span of the entire workload as the training objective. Additionally, effective exploration and experience replay techniques are applied to obtain effectively converged agent. To evaluate the capability of FARS, we design extensive trace-based simulation experiments with the popular DLT workloads. The experimental results show that, compared with the best baseline model, FARS obtains 5.69% improvement of average make-span under different device error rates. Together, our FARS is an ideal candidate for failure-aware job scheduler in HPC clusters. © 2021 IEEE.

关键词： Scheduling

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A Robust and Power-Effcient SoC Implementation in 65nm

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Journal of computer Science & technology 2013年第4期28卷 682-688页

作者：肖斌张译夫高燕萍杨梁吴冬梅范宝峡 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Loongson Technology Corporation Limited

Godson2H is a complex SoC （system-on-Chip） of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.

关键词： system-on-Chip on-chip-variation PVT detector low power hierarchical design flow

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Outlier detection for learning-based optimizing compiler

Outlier detection for learning-based optimizing compiler

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International Conference on Frontier of computer Science and technology

作者： Long, Shun Zhu, Weiheng Department Ofcomputer Science JiNan University Guangzhou China Key-Laboratory Ofcomputer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9780769541396

Modern compilers use machine learning to find from their prior experience useful heuristics for new programs encountered in order to accelerate the optimization process. However, prior experience might not be applicable for outlier programs with unfamiliar code features. This paper presents a Reverse K-nearest neighbor (RKNN) algorithm based approach for outlier detection. The compiler can therefore launch a search within an optimization space when outlier programs are encountered, or directly apply its experience to non-outliers. Preliminary experimental results demonstrate the effectiveness of the approach. © 2010 IEEE.

关键词： Statistics

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A Hybrid Circular Queue Method for Iterative Stencil Computations on GPUs

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Journal of computer Science & technology 2012年第1期27卷 57-74页

作者： Yang Yang Hui-Min Cui Xiao-Bing Feng Jing-Ling Xue State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Programming Languages and Compilers Group School of Computer Science and Engineering University of New South WalesSydneyNSW 2052Australia

In this paper, we present a hybrid circular queue method that can significantly boost the performance of stencil computations on GPU by carefully balancing usage of registers and shared-memory. Unlike earlier methods that rely on circular queues predominantly implemented using indirectly addressable shared memory, our hybrid method exploits a new reuse pattern spanning across the multiple time steps in stencil computations so that circular queues can be implemented by both shared memory and registers effectively in a balanced manner. We describe a framework that automatically finds the best placement of data in registers and shared memory in order to maximize the performance of stencil computations. Validation using four different types of stencils on three different GPU platforms shows that our hybrid method achieves speedups up to 2.93X over methods that use circular queues implemented with shared-memory only.

关键词： stencil computation circular queue GPU occupancy register

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A mutation-based fault injection method for C program

A mutation-based fault injection method for C program

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International Conference on Multimedia, Communication and computing Application, MCCA 2014

作者： Song, H. Wang, Y.W. Qian, G.N. Gong, Y.Z. Wang, Y.W. State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781138027756

Fault injection plays a critical role in the verification of software’s reliability. This paper presents a fault injection method by mutation. Moreover, a strategy of using semantic-based mutators is proposed to improve the efficiency of mutation testing. We implemented the method in FIT, an automatic fault injection tool. Experiments prove that the method is effective and the tool can produce lots of mutants which show that mutation testing is satisfying. © 2015 Taylor & Francis Group, London.

关键词： Semantics

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A method of stub generation for I/O functions in automatic test

A method of stub generation for I/O functions in automatic t...

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International Conference on Multimedia, Communication and computing Application, MCCA 2014

作者： Yang, Y.W. Wang, Y.W. Gong, Y.Z. Wang, Y.W. State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781138027756

Library functions and system calls have been major difficulties faced by automatic test. Input/ output (I/O) functions are a set of common library functions. Testers have to interact with the test procedures if the test program contains I/O functions, resulting in inefficient automatic test. Unlike normal functions, the association between I/O functions and operating on a specific I/O device makes ordinary stub method disabled. Aiming at solving this problem, this paper proposes one solution by I/O device modeling and I/O function modeling. The semantics of the I/O functions are stored in the I/O function model, and the operations of I/O functions are similar to the I/O device model. The final state and properties of the I/O device are represented by two models. Finally the stub code is automatically generated by path-oriented stub generation technology. Experiments show that this method is effective. © 2015 Taylor & Francis Group, London.

关键词： Semantics

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H-DB: Yet another big data hybrid system of Hadoop and DBMS

H-DB: Yet another big data hybrid system of Hadoop and DBMS

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13th International Conference on Algorithms and architectures for Parallel Processing, ICA3PP 2013

作者： Luo, Tao Chen, Guoliang Zhang, Yunquan School of Computer Science and Technology University of Science and Technology of China 230027 Hefei China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS 100190 Beijing China

ISBN: (纸本)9783319038582

With the explosion of the amount of data, analytics applications require much higher performance and scalability. However, traditional DBMS encounters the tough obstacle of scalability, and could not handle big data easily. In the meantime, due to the complex relational data model, the large amount of historical data and the independent demand of subsystems, it is not suitable to use either shared-nothing MPP architecture (e.g. Hadoop) or existing hybrid architecture (e.g. HadoopDB) to replace completely. In this paper, considering the feasibility and versatility of building a hybrid system, we propose a novel prototype H-DB which takes DBMSs as the underlying storage and execution units, and Hadoop as an index layer and a cache. H-DB not only retains the analytical DBMS, but also could handle the demands of rapidly exploding data applications. The experiments show that H-DB meets the demand, outperforms original system and would be appropriate for analogous big data applications. © Springer International Publishing Switzerland 2013.

关键词： Database systems

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An efficient methodology for power modeling and simulation of modern cell-based microprocessors

An efficient methodology for power modeling and simulation o...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Ge Zhang Weiwu Hu Institute of Computing Technology Key Laboratory of Computer System and Architecture Beijing China

This paper presents a methodology for high-level power modeling of cell-based processors. A flexible power model library, which can automatically generate detailed power data for actual circuits of each part of given processor, is developed and annotated dynamically for architecture-level power simulator. According to this method, the dynamic power, leakage power and even area and cell counts can be accurately estimated, and the preliminary power validation for a MIPS microprocessor proves our methodology to be effective and highly correlated, with only small errors comparing with the gate-level power analysis.

关键词： Microprocessors Circuit simulation Libraries Adders Circuit synthesis Power system modeling Analytical models Content addressable storage Power generation Flexible printed circuits

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Design automation methodology from RTL to gate-level netlist and schematic for RSFQ logic circuits 20

Design automation methodology from RTL to gate-level netlist...

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30th Great Lakes Symposium on VLSI, GLSVLSI 2020

作者： Fu, Rongliang Zhang, Zhi-Min Tang, Guang-Ming Huang, Junying Ye, Xiao-Chun Fan, Dong-Rui Sun, Ning-Hui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450379441

The superconducting rapid single flux quantum (RSFQ) logic circuit has the characteristics of high speed and low power consumption, making it an attractive candidate for future supercomputers. However, computer-aided design (CAD) tools for CMOS cannot be directly applied to RSFQ logic due to their distinct properties. For instance, the RSFQ logic gate can work properly when all its fan-ins have the same logic level. This paper presents the design flow from RTL to RSFQ logic netlist and schematic. First, we implement logic synthesis for RSFQ logic circuits. It achieves path balancing while minimizing the number of DFFs. In addition, we propose an automatic schematic generator for the RSFQ logic circuits. It converts the synthesized netlist into its equivalent schematic. A layer assignment algorithm is proposed, which makes all gates layered in the order of the clock arrival time. Experimental results with ISCAS85 and EPFL benchmarks along with some Kogge-Stone adders have shown a 29.2% reduction in the number of DFFs over the breadth-first first search;moreover, 59.57% and 5.3% decrease in the number of layers of the schematic and number of edge crossings over the ELK tool. © 2020 Association for computing Machinery.

关键词： Logic circuits

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