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International Journal of Database Theory and Application 2014年第1期7卷 11-24页

作者： Xing, Ying Gong, Yun-Zhan Wang, Ya-Wen Zhang, Xu-Zhou State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing100876 China Liaoning Technical University Huludao 125105 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Path-oriented test data generation is in essence a Constraint Satisfaction Problem solved by search strategies, among which backtracking algorithms are widely used. In this paper, the backtracking algorithm Branch & Bound is introduced to generate path-oriented test data automatically. A model based on state space search is proposed to construct the search tree dynamically. Aiming at the programs containing constraints of strongly related variables even equalities, the static analysis technique interval arithmetic is optimized for the precise judgment of the assignment to each variable. The analysis on conflict is made accurate via distance for further domain reduction, thus ensuring the precise direction of the next search step. Experiments show that the proposed method outperformed other methods used in static test data generation. Specifically, it produces excellent results when variables are strongly related even when they are in equalities, and generation time increases stably and linearly with the increment of number of expressions including both equalities and inequalities.© 2014 SERSC.

关键词： Constraint satisfaction problems

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HPPNetSim: A parallel simulation of large-scale interconnection networks

HPPNetSim: A parallel simulation of large-scale interconnect...

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42nd Annual Simulation Symposium 2009, ANSS 2009, Part of the 2009 Spring Simulation Multiconference

作者： Cao, Zheng Xu, Jianwei Chen, Mingyu Zheng, Gui Lv, Huiwei Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781617386404

As the scale of parallel machine grows, communication network is playing more important role than ever before. Communication affects not only execution time, but also scalability of parallel applications. Parallel interconnection network simulator is a suitable tool to study large-scale interconnection networks. However, simulating packet level communication on detailed cycle-to-cycle network models is a really challenge work. We implement a kernel-based parallel simulator HPPNetSim to solve problems. Optimistic PDES mechanism needs huge memory consumption of saving simulation entities' states in large-scale simulations, so we chose conservative synchronization approach. Simulation kernel and network models are all carefully designed. To accelerate process of simulation, optimizations are introduced, such as block/unblock synchronization, load balancing, dynamic look-ahead generation, and etc. Simulation examples and performance results show that both high accuracy and good performance are obtained in HPPNetSim. It achieves speedup of 19.8 for 32 processing nodes when simulating 36-port 3-tree fat-tree network.

关键词： Discrete event simulation

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A case study of improving at-speed testing coverage of a gigahertz microprocessor

A case study of improving at-speed testing coverage of a gig...

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2009 16th IEEE International Conference on Electronics, Circuits and systems, ICECS 2009

作者： Qi, Zichu Liu, Hui Li, Xiangku Xu, Jun Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences PO Box 2704-25 Beijing 100190 China Beijing China Loongson Technologies Corporation Limited China

ISBN: (纸本)9781424450916

For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (Random Access Memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing X states for registers, sequential bypass of macros, clock control scheme for inter-clock domains and accurate analysis of exception paths in intra-clock domains. Functional patterns are utilized to further improv. The efficiency oy the at-speed testing. A novel optimal flow is presented by carefully selecting these techniques. By usin. The flow, 90% transition fault coverage is achieved. In addition, bot. The number of patterns an. The test time oy the transition test are decreased by 15%. The total area overhead is about a few hundreds of AND cells and has little timing impact oy the critical paths. © 2009 IEEE.

关键词： Random access storage

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LINEAR SYMMETRIC QUANTIZATION OF NEURAL NETWORKS FOR LOW-PRECISION INTEGER HARDWARE 8

LINEAR SYMMETRIC QUANTIZATION OF NEURAL NETWORKS FOR LOW-PRE...

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8th International Conference on Learning Representations, ICLR 2020

作者： Zhao, Xiandong Wang, Ying Cai, Xuyi Liu, Cheng Zhang, Lei Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China State Key Laboratory of Computer Architecture China

With the proliferation of specialized neural network processors that operate on low-precision integers, the performance of Deep Neural Network inference becomes increasingly dependent on the result of quantization. Despite plenty of prior work on the quantization of weights or activations for neural networks, there is still a wide gap between the software quantizers and the low-precision accelerator implementation, which degrades either the efficiency of networks or that of the hardware for the lack of software and hardware coordination at design-phase. In this paper, we propose a learned linear symmetric quantizer for integer neural network processors, which not only quantizes neural parameters and activations to low-bit integer but also accelerates hardware inference by using batch normalization fusion and low-precision accumulators (e.g., 16-bit) and multipliers (e.g., 4-bit). We use a unified way to quantize weights and activations, and the results outperform many previous approaches for various networks such as AlexNet, ResNet, and lightweight models like MobileNet while keeping friendly to the accelerator architecture. Additional, we also apply the method to object detection models and witness high performance and accuracy in YOLO-v2. Finally, we deploy the quantized models on our specialized integer-arithmetic-only DNN accelerator to show the effectiveness of the proposed quantizer. We show that even with linear symmetric quantization, the results can be better than asymmetric or non-linear methods in 4-bit networks. In evaluation, the proposed quantizer induces less than 0.4% accuracy drop in ResNet18, ResNet34, and AlexNet when quantizing the whole network as required by the integer processors. © 2020 8th International Conference on Learning Representations, ICLR 2020. All rights reserved.

关键词： Chemical activation

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Analysis and mitigation of function interaction risks in robot apps 21

Analysis and mitigation of function interaction risks in rob...

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24th International Symposium on Research in Attacks, Intrusions and Defenses, RAID 2021

作者： Xu, Yuan Zhang, Tianwei Bao, Yungang State Key Laboratory of Computer Architecture Institute of Computing Technology University of Chinese Academy of Sciences Peng Cheng Laboratory China Nanyang Technological University China

ISBN: (纸本)9781450390583

Robot apps are becoming more automated, complex and diverse. An app usually consists of many functions, interacting with each other and the environment. This allows robots to conduct various tasks. However, it also opens a new door for cyber attacks: adversaries can leverage these interactions to threaten the safety of robot operations. Unfortunately, this issue is rarely explored in past works. We present the first systematic investigation about the function interactions in common robot apps. First, we disclose the potential risks and damages caused by malicious interactions. By investigating the relationships among different functions, we identify and categorize three types of interaction risks. Second, we propose RTron, a novel system to detect and mitigate these risks and protect the operations of robot apps. We introduce security policies for each type of risks, and design coordination nodes to enforce the policies and regulate the interactions. We conduct extensive experiments on 110 robot apps from the ROS platform and two complex apps (Baidu Apollo and Autoware) widely adopted in industry. Evaluation results indicated RTron can correctly identify and mitigate all potential risks with negligible performance cost. To validate the practicality of the risks and solutions, we implement and evaluate RTron on a physical UGV (Turtlebot) with real-word apps and environments. © 2021 ACM.

关键词： Risk analysis

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A testability-aware low power architecture

A testability-aware low power architecture

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25th IEEE International system-on-Chip Conference, SOCC 2012

作者： Wang, Gang Wang, Jian Qi, Zi-Chu Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China

ISBN: (纸本)9781467312950

Test power consumption is becoming a major concern in low power integrated circuits(ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption. © 2012 IEEE.

关键词： Electric power utilization

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Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators 27

Leveraging FVT-margins in design space exploration for FFGA-...

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27th International Conference on Field Programmable Logic and Applications, FPL 2017

作者： Lu, Weina Lu, Wenyan Ye, Jing Hu, Yu Li, Xiaowei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China

ISBN: (纸本)9789090304281

The performance of an FPGA based CNN accelerator is determined by both parallelism and frequency, however, most prior works optimize the parallelism in the RTL design and resolve the frequency after the synthesis. This paper presents a design space exploration method for the pipeline implementation of the deep CNN models, which concurrently optimizes parallelism and frequency to achieve a comprehensive optimization on throughput. In addition to the quantitative modeling on parallelism, the maximum achievable system frequency under various parallelism is explored to leverage the PVT-margins in real-life scenarios and is adopted to guide the design space exploration for further performance boost. A case study of the AlexNet model is implemented using the proposed method on the Altera DE5a-Net board. The experimental results demonstrate that our method can achieve the throughput up to 906.25GOP/s, which gains 1.39× improvement compared to state-of-the-art RTL optimization methods. © 2017 Ghent University.

关键词： Network architecture

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A processor-DMA-based memory copy hardware accelerator

A processor-DMA-based memory copy hardware accelerator

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IEEE International Conference on Networking, architecture and Storage

作者： Su, Wen Wang, Ling Su, Menghao Liu, Su Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769545097

For many Operating systems and device drivers, memory copy is the most time-consuming operation which has always been paid special attention. In this paper, we propose a processor DMA based memory copy hardware accelerator with the goal to reduce the instructions executed on CPU, and exploit the parallelism between computing and data transfer in memory copy. This is accomplished by taking advantage of a proposed Direct Memory Access (DMA) engine in the processor which overcomes many conventional DMA engine shortcomings. Experimental results show that the proposed hardware solution achieves a speedup of 14.79 compared with the optimized software solution and an overlap of 81.8% in computing and data transfer on average. © 2011 IEEE.

关键词： Engines

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Construction of Traditional Culture Ontology Based on Representation and Role 23

Construction of Traditional Culture Ontology Based on Repres...

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2023 4th International Conference on Control, Robotics and Intelligent system, CCRIS 2023

作者： Li, Min Xu, Jianliang Wu, Xiaoquan Ocean University of China Qingdao China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Qingdao China

ISBN: (纸本)9798400708190

Traditional culture refers to a culture that has evolved from civilization and can reflect the characteristics and spirit of a nation. However, at present, the traditional cultural ontology only focuses on modeling and data organization of a certain type of traditional culture, which is a certain distance from the massive cultural information and urgent cultural needs. This article starts from the perspective of protecting and inheriting traditional culture, and based on representation, incorporates role theory to construct a cultural ontology centered on poetry, calligraphy, and painting. The traditional cultural ontology constructed in this article can further contribute to the field of artificial intelligence. © 2023 ACM.

关键词： Ontology

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A lightweight hybrid hardware/software approach for object-relative memory profiling

A lightweight hybrid hardware/software approach for object-r...

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2012 IEEE International Symposium on Performance Analysis of systems and Software, ISPASS 2012

作者： Chen, Licheng Cui, Zehan Bao, Yungang Chen, Mingyu Huang, Y. Tan, Guangming State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School of Chinese Academy of Sciences China

ISBN: (纸本)9781467311441

Memory profiling is the process of collecting memory address traces during the execution of a program, then analyzing and characterizing the memory behavior of the program offline. With the trend that there will be more and more cores integrated in a processor chip, the Memory Wall problem will become more serious in the chip multiprocessor (CMP) system. Thus accurate and effective memory profiling is becoming one of the keys to identify the source of memory system bottlenecks. A large body of work has been contributed to memory profiling, however, most adopts instrumentation, simulator which suffers heavy overhead, or hardware performance counter which is lack of detail trace information. Furthermore, correlating the raw memory address traces with object-relative information allows us to separate regular pattern for certain object from the irregular mixed, thus helps the optimization. In this paper, we propose a lightweight hybrid hardware/software approach for object-relative memory profiling. We monitor physical memory addresses through hardware snooping with negligible overhead;meanwhile we dump Linux kernel page tables of processes, as well as object-relative memory allocation information. Our approach supports not only to collect applications' full memory traces with detail object relative information, but also to identify hardware-generated memory accesses such as page memory walks due to TLB miss at object level. The experimental results on real system show that our approach is highly accurate (the largest error is 2.04%) and low overhead (the average overhead is 1.60%). Furthermore, we profile two multi-thread applications in detail, and successfully identity hot TLB-miss objects. With object-targeted optimization, we can improve applications' performance by nearly 6.86%. © 2012 IEEE.

关键词： computer operating systems

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