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作者： Pan, Songjun Hu, Yu Hu, Xing Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution;2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies;3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach. © 2011 EDAA.

关键词： Cost effectiveness

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An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits

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Frontiers of computer Science 2017年第4期11卷 728-742页

作者： Zhenxue HE Limin XIAO Fei GU Tongsheng XIA Shubin SU Zhisheng HUO Rong ZHANG Longbing ZHANG Li RUAN Xiang WANG State Key Laboratory of Software Development Environment Beihang University Beijing 100191 China School of Computer Science and Engineering Beihang University Beijing 100191 China School of Electronic and Information Engineering Beihang University Beijing 100191 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China National Engineering Research Center for Science & Technology Resources Sharing Service Beijing 100191 China

Although the genetic algorithm has been widely used in the polarity optimization of mixed polarity Reed- Muller （MPRM） logic circuits, few studies have taken into account the polarity conversion sequence. In order to im- prove the efficiency of polarity optimization of MPRM logic circuits, we propose an efficient and fast polarity optimiza- tion approach （FPOA） considering the polarity conversion se- quence. The main idea behind the FPOA is that, firstly, the best polarity conversion sequence of the polarity set wait- ing for evaluation is obtained by using the proposed hybrid genetic algorithm （HGA）; secondly, each of polarity in the polarity set is converted according to the best polarity con- version sequence obtained by HGA. Our proposed FPOA is implemented in C and a comparative analysis has been pre- sented for MCNC benchmark circuits. The experimental re- suits show that for the circuits with more variables, the FPOA is highly effective in improving the efficiency of polarity op- timization of MPRM logic circuits compared with the tradi- tional polarity optimization approach which neglects the po- larity conversion sequence and the improved polarity opti- mization approach with heuristic technique.

关键词： genetic algorithm polarity optimization mixed

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Optimizing sparse matrix vector multiplication using cache blocking method on Fermi GPU

Optimizing sparse matrix vector multiplication using cache b...

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13th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed computing, SNPD 2012

作者： Xu, Weizhi Zhang, Hao Jiao, Shuai Wang, Da Song, Fenglong Liu, Zhiyong Key Lab. of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769547619

It is an important task to tune performance for sparse matrix vector multiplication (SpMV), but it is also a difficult task because of its irregularity. In this paper, we propose a cache blocking method to improve the performance of SpMV on the emerging GPU architecture. The sparse matrix is partitioned into many sub-blocks, which are stored in CSR format. With the blocking method, the corresponding part of vector x can be reused in the GPU cache, so the time spent on accessing the global memory for vector x is reduced heavily. Experimental results on GeForce GTX 480 show that SpMV kernel with the cache blocking method is 5x faster than the unblocked CSR kernel in the best case. © 2012 IEEE.

关键词： Graphics processing unit

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A New Post-Silicon Debug Approach Based on Suspect Window

A New Post-Silicon Debug Approach Based on Suspect Window

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IEEE VLSI Test Symposium (VTS)

作者： Jianliang Gao Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781424437696

Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. Then we introduce "suspect window" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain. Since scan dumps take place only in suspect window, debug time is greatly reduced. Experimental results demonstrate the effectiveness of the proposed approach.

关键词： Post-silicon debug Suspect window Trace Scan Bug

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A Case Study: Low Power Design-for-Testability Features of a Multi-core Processor Godson-T

A Case Study: Low Power Design-for-Testability Features of a...

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2011 2nd International Conference on Advanced Measurement and Test (AMT 2011)

作者： Da Wang Dongrui Fan Yu Hu Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical coresSince the silicon design technology scales to ultra deep submicron and even nanometers, the complexity and cost of testing is growing up, and the test power of such designs is extremely curious, especially for multicore processorsIn this paper, we use the modular design methodology and scaleable design-for-testability(DFT) structure to achieve low test power, at the same time, an improved test pattern generation method is studied to reduce test power further moreThe experimental results from the real chip show that the test power and test time are well balanced while achieving acceptable test coverage and cost.

关键词： design-for-testability(DFT),multi-core processor,very large scale integration(VLSI),power reduction,pattern filling,multi-capture

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Communication Lower Bounds of Convolutions in CNNs 20

Communication Lower Bounds of Convolutions in CNNs

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32nd ACM Symposium on Parallelism in Algorithms and architectures, SPAA 2020

作者： Zhang, Xiaoyang Xiao, Junmin Tan, Guangming State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Science Beijing China

ISBN: (纸本)9781450369350

Convolution is the most time-consuming part in the computation of convolutional neural networks (CNNs). Due to the complex data dependency and the increase in the amount of model samples, the convolution suffers from high overhead on data movement. This work provides comprehensive analysis and methodologies to minimize the communication for the convolutions in CNNs. With an in-depth analysis on the I/O complexity theory under the red-blue pebble game model, we develop a general communication lower bound theory for a composite algorithm which consists of several different sub-computations. Based on the proposed theory, we establish the data movement lower bound results for three main convolution algorithms in CNNs, which are the direct convolution, the image2col method and Winograd algorithm. Furthermore, derived from I/O lower bound results, we design the near communication-optimal strategies respectively for the three main convolution algorithms by fully exploiting the data reuse. The deep analysis demonstrates that our designs are able to nearly reach the minimum communication in a two-level memory hierarchy. © 2020 Owner/Author.

关键词： Convolution

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RSAK: Random stream attack for phase change memory in video applications

RSAK: Random stream attack for phase change memory in video ...

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2013 IEEE 31st VLSI Test Symposium, VTS 2013

作者： Fang, Yuntan Li, Huawei Li, Xiaowei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781467355438

As an emerging non-volatile memory technology, phase change memory (PCM) is promising as an alternative for traditional memories such as DRAM. In spite of its non-volatility, high density, low standby power, and resilience to soft errors, PCM has a limited write endurance or lifetime, which means that each PCM cell can only be overwritten finite times. More importantly, limited lifetime potentially provides malicious attackers an opportunity to intentionally aggravate write traffic into PCM. In this paper, from the standpoint of attackers, we propose random stream attacks (RSAK) methods for phase change memory used in video applications. Experimental results show that compared to natural video sequences, RSAK incurs higher total write traffic or worsened lifetime. RSAK also gives hints on how to build a more secure PCM in video applications to counter malicious write streams. © 2013 IEEE.

关键词： Phase change memory

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Road type estimation and hierarchical real-time vanishing point detection

Road type estimation and hierarchical real-time vanishing po...

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2013 7th International Conference on Image and Graphics, ICIG 2013

作者： Sun, Yuan Lu, Hongbo Zhang, Zhimin .State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China .University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769550503

Image-based road vanishing point (VP) detection is a challenging problem as the algorithm needs to deal with different road type with varying imaging conditions in real time. We propose a hierarchical VP detection method with the ability to choose efficient algorithms for different road types. Firstly, road scenes are classified into 4 types based on holistic road features abstracted from responses of Gabor filters, which also coarsely locate the road. Then, the distinct edge or line-like texture of each road type is adaptively extracted by a new road-line-segment detection method. Finally, VP is estimated by road-type-specific voting and verification. Experiments on 1000 general road images show that, the proposed method can detect VP under complex road scenes, achieving improvements for both accuracy and efficiency, compared with the state of the art methods relying on single features. © 2013 IEEE.

关键词： Gabor filters

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An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects 12

An efficient parity rearrangement coding scheme for RRAM the...

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2017 IEEE 12th International Conference on ASIC

作者： Yun Li Hai-hua Shen Ce Li Feng Zhang Key Laboratory of Microelectronics devices & Integrated Techonology Institute of Microelectronics of Chinese Academy of Sciences University of Chinese Academy of Science State Key Laboratory of Computer Architecture University of Chinese Academy of Science Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781509066261;9781509066254

Resistive random access memory（RRAM） is a promising non-volatile memory owing to its low operation voltage,small area,and good ***,the thermal crosstalk issue will significantly impact the retention properties of RRAM for high density integration and frequent writing operation,which commonly causes a series of error flips in some serious *** this paper,we propose an efficient parity rearrangement coding scheme,named PRCoder,to alleviate the influence of thermal crosstalk in *** implement the PRCoder at the algorithm level and simulated it at the hardware circuits level for different RRAM *** show that PRCoder can reduce the error flips caused by thermal crosstalk by about 32.7% on average with only one extra bit of redundancy per storage ***,PRCoder incurs a negligible performance overhead of .3% with less than 0.008% additional RRAM area.

关键词： RRAM thermal crosstalk PRCoder reset parity rearrangement algorithm

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Micro-architectural characterization of desktop cloud workloads

Micro-architectural characterization of desktop cloud worklo...

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2012 IEEE International Symposium on Workload Characterization, IISWC 2012

作者： Jiang, Tao Hou, Rui Zhang, Lixin Zhang, Ke Chen, Licheng Chen, Mingyu Sun, Ninghui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781457720642

Desktop cloud replaces traditional desktop computers with completely virtualized systems from the cloud. It is becoming one of the fastest growing segments in the cloud computing market. However, as far as we know, there is little work done to understand the behavior of desktop cloud. On one hand, desktop cloud workloads are different from conventional data center workloads in that they are rich with interactive operations. Desktop cloud workloads are different from traditional non-virtualized desktop workloads in that they have an extra layer of software stack - hypervisor. On the other hand, desktop cloud servers are mostly built with conventional commodity processors. While such processors are well optimized for traditional desktops and high performance computing workloads, their effectiveness for desktop cloud workloads remains to be studied. As an attempt to shed some lights on the effectiveness of conventional general-purpose processors on desktop cloud workloads, we have studied the behavior of desktop cloud workloads and compared it with that of SPEC CPU2006, TPC-C, PARSEC, and CloudSuite. We evaluate a Xen-based virtualization platform. The performance results reveal that desktop cloud workloads have significantly different characteristics with SPEC CPU2006, TPC-C and PARSEC, but they perform similarly with data center scale-out benchmarks from CloudSuite. In particular, desktop cloud workloads have high instruction cache miss rate (12.7% on average), high percentage of kernel instructions (23%, on average), and low IPC (0.36 on average). And they have much higher TLB miss rates and lower utilization of off-chip memory bandwidth than traditional benchmarks. Our experimental numbers indicate that the effectiveness of existing commodity processors is quite low for desktop cloud workloads. In this paper, we provide some preliminary discussions on some potential architectural and micro-architectural enhancements. We hope that the performance numbers presented i

关键词： Personal computers

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