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Green challenges to system software in data centers

中国计算机科学前沿 2011年第3期5卷 353-368页

作者： Yuzhong SUN Yiqiang ZHAO Ying SONG Yajun YANG Haifeng FANG Hongyong ZANG Yaqiong LI Yunwei GAO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100190 China

With the increasing demand and the wide application of high performance commodity multi-core processors,both the quantity and scale of data centers grow dramatically and they bring heavy energy *** and engineers have applied much effort to reducing hardware energy consumption,but software is the true consumer of power and another key in making better use of *** software is critical to better energy utilization,because it is not only the manager of hardware but also the bridge and platform between applications and *** this paper,we summarize some trends that can affect the efficiency of data ***,we investigate the causes of software *** on these studies,major technical challenges and corresponding possible solutions to attain green system software in programmability,scalability,efficiency and software architecture are ***,some of our research progress on trusted energy efficient system software is briefly introduced.

关键词： green software multi-core data center power efficient system software

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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

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Journal of computer Science & technology 2008年第6期23卷 1037-1046页

作者：王达胡瑜李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.

关键词： microprocessor design-for-testability test generation built-in self-test at-speed testing

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Landing Stencil Code on Godson-T

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Journal of computer Science & technology 2010年第4期25卷 886-894页

作者：崔慧敏王蕾范东睿冯晓兵 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

The advent of multi-core/many-core chip technology offers both an extraordinary opportunity and a profound challenge. In particular, computer architects and system software designers are faced with a unique opportunity to introducing new architecture features as well as adequate compiler technology -- together they may have profound impact. This paper presents a case study （using the 1-D Jacobi computation） of compiler-amendable performance optimization techniques on a many-core architecture Godson-T. Godson-T architecture has several unique features that are chosen for this study： 1） chip-level global addressable memory in particular the scratchpad memories （SPM） local to the processing cores; 2） fine-grain memory based synchronization （e.g., full-empty bit for fine-grain synchronization）. Leveraging state-of-the-art performance optimization methods for 1-D stencil parallelization （e.g., timed tiling and variants）, we developed and implement a number of many-core-based optimization for Godson-T. Our experimental study shows good performance in both execution time speedup and scalability, validate the value of globally accessed SPM and fine-grain synchronization mechanism （full-empty bits） under the Godson-T, and provides some useful guidelines for future compiler technology of many-core chip architectures.

关键词： many-core, stencil, Jacobi, compiler SPM, fine-grain synchronization

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Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

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Journal of computer Science & technology 2009年第6期24卷 1074-1085页

作者：张颖李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate School of the Chinese Academy of Sciences

With the shrink of the technology into nanometer scale, network-on-chip （NOC） has become a reasonable solution for connecting plenty of IP blocks on a single chip. But it suffers from both crosstalk effects and single event upset （SEU）, especially crosstalk-induced delay, which may constrain the overall performance of NOC. In this paper, we introduce a reliable NOC design using a code with the capability of both crosstalk avoidance and single error correction. Such a code, named selected crosstalk avoidance code （SCAC） in our previous work, joins crosstalk avoidance code （CAC） and error correction code （ECC） together through codeword selection from an original CAC codeword set. It can handle possible error caused by either crosstalk effects or SEU. When designing a reliable NOC, data are encoded to SCAC codewords and can be transmitted rapidly and reliably across NOC. Experimental results show that the NOC design with SCAC achieves higher performance and is reliable to tolerate single errors. Compared with previous crosstalk avoidance methods, SCAC reduces wire overhead, power dissipation and the total delay. When SCAC is used in NOC, it can save 20% area overhead and reduce 49% power dissipation.

关键词： crosstalk avoidance codeword selection reliable network-on-chip single event upset

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E2DAS: An Efficient Equivariant Dynamic Aggregation Saliency Model for Omnidirectional Images 27th

E2DAS: An Efficient Equivariant Dynamic Aggregation Saliency...

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27th International Conference on Pattern Recognition, ICPR 2024

作者： Zhang, Nana Liu, Qian Zhu, Dandan Zhu, Kun Zhai, Guangtao Yang, Xiaokang School of Computer Science and Technology Donghua University No.2999 Renmin North Road Songjiang District Shanghai201620 China Institute of AI Education Shanghai East China Normal University No.3663 Zhongshan North Road Putuo District Shanghai200333 China Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University No.4800 Cao’an Highway Jiading District Shanghai201804 China Institute of Image Communication and Network Engineering Shanghai Jiao Tong University No. 800 Dongchuan Road Minhang District Shanghai200240 China

ISBN: (纸本)9783031781216

Recent years have witnessed rapid progress of convolutional neural networks (CNNs) and their successful application in the task of saliency prediction for omnidirectional images (ODIs). Albeit achieving tremendous performance improvements, these CNNs-based saliency models are plagued by two major shortcomings: spatial content-agnostic and computationally intensive. Inspired by the effectiveness of equivariant network in the majority of computer vision tasks, we propose a novel efficient equivariant dynamic aggregation saliency (E2DAS) model to efficiently tackle the issue of human fixation prediction in ODIs. To be specific, our proposed model consists of an efficient equivariant module, a dynamic convolutional aggregation module, and an optimization computation module. Different from existing saliency models for ODIs, we are the first attempt to introduce an efficient equivariant dynamic convolutional aggregation operation into the saliency prediction task, which can fundamentally alleviate the projection distortion problem and can effectively learn spatial content-adaptive features. Moreover, we clearly observe a considerable decrease in the number of parameters resulting from the replacement of standard convolution with dynamic convolution aggregation. Extensive experiments on several benchmark datasets show the proposed model’s superiority over other state-of-the-art methods in terms of performance. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Equivariant dynamic aggregation light-weight model omnidirectional images saliency prediction spatial content-adaptive

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Godson-T:An Efficient Many-Core architecture for Parallel Program Executions

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Journal of computer Science & technology 2009年第6期24卷 1061-1073页

作者：范东睿袁楠张军超周永彬林伟宋风龙叶笑春黄河余磊龙国平张浩刘磊 Key Laboratory of Computer Systems and Architecture Institute of Computing Technology Chinese Academy of Sciences

Moore＇s law will grant computer architects ever more transistors for the foreseeable future, and the challenge is how to use them to deliver efficient performance and flexible programmability. We propose a many-core architecture, Godson- T, to attack this challenge. On the one hand, Godson-T features a region-based cache coherence protocol, asynchronous data transfer agents and hardware-supported synchronization mechanisms, to provide full potential for the high efficiency of the on-chip resource utilization. On the other hand, Godson-T features a highly efficient runtime system, a Pthreadslike programming model, and versatile parallel libraries, which make this many-core design flexibly programmable. This hardware/software cooperating design methodology bridges the high-end computing with mass programmers. Experimental evaluations are conducted on a cycle-accurate simulator of Godson-T. The results show that the proposed architecture has good scalability, fast synchronization, high computational efficiency, and flexible programmability.

关键词： many-core parallel computing multithread data communication thread synchronization runtime system

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Online Distributed Fault Detection of Sensor Measurements

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Tsinghua Science and technology 2007年第S1期12卷 192-196页

作者：高建良徐勇军李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may make inappropriate decisions when it receives the incorrect data sent by the faulty sensors. To solve these problems, this paper develops an online distributed algorithm to detect such faults by exploring the weighted majority vote scheme. Considering the spatial correlations in WSNs, a faulty sensor can diagnose itself through utilizing the spatial and time information provided by its neighbor sensors. Simulation results show that even when as many as 30% of the sensors are faulty, over 95% of faults can be correctly detected with our algorithm. These results indicate that the proposed algorithm has excellent performance in detecting fault of sensor measurements in WSNs.

关键词： wireless sensor networks fault diagnosis fault detection fault tolerance spatial correlation

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High Performance General-Purpose Microprocessors： Past and Future

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Journal of computer Science & technology 2006年第5期21卷 631-640页

作者：胡伟武侯锐肖俊华章隆宾 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China

It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors （CMPs）. Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced.

关键词： high performance general-purpose microprocessor instruction level parallelism data level parallelism thread level parallelism chip multiprocessors Godson processor

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Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

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Journal of computer Science & technology 2007年第5期22卷 673-680页

作者：王伟胡瑜韩银和李晓维张佑生 School of Computer and Information Hefei University of Technology Hefei 230009China Key Laboratory of Computer System and ArchitectureInstitute of Computing TechnologyChinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080China School of Computer and Information Hefei University of Technology Hefei 230009China

It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,

关键词： leakage current don't care bits minimum leakage vector leakage power

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Design for Testability Features of Godson-3 Multicore Microprocessor

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Journal of computer Science & technology 2011年第2期26卷 302-313页

作者：齐子初刘慧李向库胡伟武 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences Loongson Technologies Corporation Limited

This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

关键词： DFT (design for testability) TAM (test access mechanism) multicore processor low power test

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