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27th International Conference on Field Programmable Logic and Applications, FPL 2017

作者： Lu, Weina Lu, Wenyan Ye, Jing Hu, Yu Li, Xiaowei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China

ISBN: (纸本)9789090304281

The performance of an FPGA based CNN accelerator is determined by both parallelism and frequency, however, most prior works optimize the parallelism in the RTL design and resolve the frequency after the synthesis. This paper presents a design space exploration method for the pipeline implementation of the deep CNN models, which concurrently optimizes parallelism and frequency to achieve a comprehensive optimization on throughput. In addition to the quantitative modeling on parallelism, the maximum achievable system frequency under various parallelism is explored to leverage the PVT-margins in real-life scenarios and is adopted to guide the design space exploration for further performance boost. A case study of the AlexNet model is implemented using the proposed method on the Altera DE5a-Net board. The experimental results demonstrate that our method can achieve the throughput up to 906.25GOP/s, which gains 1.39× improvement compared to state-of-the-art RTL optimization methods. © 2017 Ghent University.

关键词： Network architecture

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An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits

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Frontiers of computer Science 2017年第4期11卷 728-742页

作者： Zhenxue HE Limin XIAO Fei GU Tongsheng XIA Shubin SU Zhisheng HUO Rong ZHANG Longbing ZHANG Li RUAN Xiang WANG State Key Laboratory of Software Development Environment Beihang University Beijing 100191 China School of Computer Science and Engineering Beihang University Beijing 100191 China School of Electronic and Information Engineering Beihang University Beijing 100191 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China National Engineering Research Center for Science & Technology Resources Sharing Service Beijing 100191 China

Although the genetic algorithm has been widely used in the polarity optimization of mixed polarity Reed- Muller （MPRM） logic circuits, few studies have taken into account the polarity conversion sequence. In order to im- prove the efficiency of polarity optimization of MPRM logic circuits, we propose an efficient and fast polarity optimiza- tion approach （FPOA） considering the polarity conversion se- quence. The main idea behind the FPOA is that, firstly, the best polarity conversion sequence of the polarity set wait- ing for evaluation is obtained by using the proposed hybrid genetic algorithm （HGA）; secondly, each of polarity in the polarity set is converted according to the best polarity con- version sequence obtained by HGA. Our proposed FPOA is implemented in C and a comparative analysis has been pre- sented for MCNC benchmark circuits. The experimental re- suits show that for the circuits with more variables, the FPOA is highly effective in improving the efficiency of polarity op- timization of MPRM logic circuits compared with the tradi- tional polarity optimization approach which neglects the po- larity conversion sequence and the improved polarity opti- mization approach with heuristic technique.

关键词： genetic algorithm polarity optimization mixed

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An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects 12

An efficient parity rearrangement coding scheme for RRAM the...

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2017 IEEE 12th International Conference on ASIC

作者： Yun Li Hai-hua Shen Ce Li Feng Zhang Key Laboratory of Microelectronics devices & Integrated Techonology Institute of Microelectronics of Chinese Academy of Sciences University of Chinese Academy of Science State Key Laboratory of Computer Architecture University of Chinese Academy of Science Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781509066261;9781509066254

Resistive random access memory（RRAM） is a promising non-volatile memory owing to its low operation voltage,small area,and good ***,the thermal crosstalk issue will significantly impact the retention properties of RRAM for high density integration and frequent writing operation,which commonly causes a series of error flips in some serious *** this paper,we propose an efficient parity rearrangement coding scheme,named PRCoder,to alleviate the influence of thermal crosstalk in *** implement the PRCoder at the algorithm level and simulated it at the hardware circuits level for different RRAM *** show that PRCoder can reduce the error flips caused by thermal crosstalk by about 32.7% on average with only one extra bit of redundancy per storage ***,PRCoder incurs a negligible performance overhead of .3% with less than 0.008% additional RRAM area.

关键词： RRAM thermal crosstalk PRCoder reset parity rearrangement algorithm

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Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack 23

Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA So...

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23rd IEEE International Symposium on On-Line Testing and Robust system Design, IOLTS 2017

作者： Ye, Jing Gong, Yue Hu, Yu Li, Xiaowei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781538603512

Physical Unclonable Function {PUF) is severely threatened by modeling attacks. This paper proposes a novel Polymorphic PUF for CPU+FPGA SoC. We fully exploit the dynamic reconfigurability of the SoC to minimize the Challenge Response Pair (CRP) correlation so as to resist modeling attacks. An asymmetric RO pair is proposed to produce the response. Experiments on real CPU+FPGA SoCs show the high resistance of Polymorphic PUF against modeling attacks, with good uniformity and uniqueness. © 2017 IEEE.

关键词： system-on-chip

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Characterizing big data analytics workloads on POWER8 SMT processors

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High technology Letters 2017年第3期23卷 245-251页

作者：贾禛 Zhan Jianfeng Wang Lei Zhang Lixin State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P. R. China University of Chinese Academy of Sciences Beijing 100049 P. R. China

Big data analytics is emerging as one kind of the most important workloads in modern data centers. Hence,it is of great interest to identify the method of achieving the best performance for big data analytics workloads running on state-of-the-art SMT( simultaneous multithreading) processors,which needs comprehensive understanding to workload characteristics. This paper chooses the Spark workloads as the representative big data analytics workloads and performs comprehensive measurements on the POWER8 platform,which supports a wide range of multithreading. The research finds that the thread assignment policy and cache contention have significant impacts on application performance. In order to identify the potential optimization method from the experiment results,this study performs micro-architecture level characterizations by means of hardware performance counters and gives implications accordingly.

关键词： simultaneous multithreading（SMT） workloads characterization POWER8 big data analytics

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A case study of 3D RTM-TTI algorithm on multicore and many-core platforms

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High technology Letters 2017年第2期23卷 185-190页

作者：张秀霞 Tan Guangming Chen Mingyu Yao Erlin State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 P. R. China University of Chinese Academy of Sciences Beijing 100049 P. R. China

3D reverse time migration in tiled transversly isotropic(3D RTM-TTI) is the most precise model for complex seismic ***,vast computing time of 3D RTM-TTI prevents it from being widely used,which is addressed by providing parallel solutions for 3D RTM-TTI on multicores and *** data parallelism and memory optimization,the hot spot function of 3D RTMTTI gains 35.99 X speedup on two Intel Xeon CPUs,89.75 X speedup on one Intel Xeon Phi,89.92 X speedup on one NVIDIA K20 GPU compared with serial CPU *** study makes RTM-TTI practical in *** the computation pattern in RTM is stencil,the approaches also benefit a wide range of stencil-based applications.

关键词： 3D RTM-TTI Intel Xeon Phi NVIDIA K20 GPU stencil computing manycore multicore seismic imaging

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XoT: A flexible block I/O data transfer protocol for xen 10th

XoT: A flexible block I/O data transfer protocol for xen

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10th International Conference on Security, Privacy and Anonymity in Computation, Communication and Storage, SpaCCS 2017

作者： Zhang, Jin Li, Yuxuan Sun, Chengjun Yang, Haoxiang Wu, Jiacheng Gong, Xiaoli College of Computer and Control Engineering Nankai University Tianjin300350 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China

ISBN: (纸本)9783319723945

The management of I/O resources is an important part of virtualization. Although the traditional management is complex, it becomes more challenging in virtualization. There has been many researches on how to improve I/O performance or fairness on Linux using extra semantic data, unfortunately many of them are not proper for virtualization. Because of the limitation of I/O protocol, such extra data can not be transferred along with device data. This forms a semantic gap between VM and hypervisor. In this paper, we proposed Xen on Turnout (XoT), a flexible block I/O data transfer protocol for Xen. XoT makes it possible to transfer extra important I/O data across the gap. We also develop a prototype to prove the effectiveness of our protocol. Our result shows that preferential effect are well achieved for user to manage block I/O with the transferred extra data, with little performance lost. © Springer International Publishing AG 2017.

关键词： Virtual machine

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New Big Data Collecting Method Based on Compressive Sensing in WSN

New Big Data Collecting Method Based on Compressive Sensing ...

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International Conference on computer Communications and Networks (ICCCN)

作者： De-gan Zhang Xiao-hua Liu Yu-ya Cui Hong-tao Peng School of Computer Science &Engineering Tianjin University of Technology Tianjin China Computing & Novel software Technology Tianjin Key Lab of Intelligent Tianjin China Ministry of Education Key Laboratory of Computer Vision and System(TJUT) Tianjin China National Petroleum Corporation (CNPC) Managers Training Institute Beijing China

Considered the wireless sensor network clustering structure, a new big data collecting method based on compressive sensing is proposed. The collection process is as follows: in the cluster, the sink node sets the corresponding seed vector based on the distribution of network, and then sends it to each cluster head. Cluster head can generate corresponding own random spacing sparse matrix based on its received seed vector, and collect data through compressive sensing technology; Among clusters, clusters forward measurement values to sink node along multi-hop routing tree which we built before. Performance analyzing and comparison of results show that this method is superior to other methods regardless of in a cluster or inter-cluster.

关键词： Wireless sensor networks Compressed sensing Sparse matrices Big Data Routing Energy consumption Training

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Balanced Quantization： An Effective and Efficient Approach toQuantized Neural Networks

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Journal of computer Science & technology 2017年第4期32卷 667-682页

作者： Shu-Chang Zhou Yu-Zhi Wang He Wen Qin-Yao He Yu-Heng Zou University of Chinese Academy of Sciences Beijing 100049 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Megvii Inc. Beijing 100190 China Department of Electronic Engineering Tsinghua University Beijing 100084 China Department of Computer Science and Technology Tsinghua University Beijing 100084 China School of Electronics Engineering and Computer Science Peking University Beijing 100871 China

Quantized neural networks (QNNs), which use low bitwidth numbers for representing parameters and performing computations, have been proposed to reduce the computation complexity, storage size and memory usage. In QNNs, parameters and activations are uniformly quantized, such that the multiplications and additions can be accelerated by bitwise operations. However, distributions of parameters in neural networks are often imbalanced, such that the uniform quantization determined from extremal values may underutilize available bitwidth. In this paper, we propose a novel quantization method that can ensure the balance of distributions of quantized values. Our method first recursively partitions the parameters by percentiles into balanced bins, and then applies uniform quantization. We also introduce computationally cheaper approximations of percentiles to reduce the computation overhead introduced. Overall, our method improves the prediction accuracies of QNNs without introducing extra computation during inference, has negligible impact on training speed, and is applicable to both convolutional neural networks and recurrent neural networks. Experiments on standard datasets including ImageNet and Penn Treebank confirm the effectiveness of our method. On ImageNet, the top-5 error rate of our 4-bit quantized GoogLeNet model is 12.7%, which is superior to the state-of-the-arts of QNNs.

关键词： quantized neural network percentile histogram equalization uniform quantization

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A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions

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Journal of computer Science & technology 2017年第2期32卷 297-311页

作者： Zhen-Xue He Li-Min Xiao Li Ruan Fei Gu Zhi-Sheng Huo Guang-Jun Qin Ming-Fa Zhu F Long-Bing Zhang Rui Liu Xiang Wang State Key Laboratory of Software Development Environment Beihang University Beijing 100191 China School of Computer Science and Engineering Beihang University Beijing 100191 China School of Electronic and Information Engineering Beihang University Beijing 100191 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China National Engineering Research Center for Science and Technology Resources Sharing Service Beihang University Beijing 100191 China

The power and area optimization of Reed-Muller （RM） circuits has been widely concerned. However, almost none of the exiting power and area optimization approaches can obtain all the Pareto optimal solutions of the original problem and are efficient enough. Moreover, they have not considered the don＇t care terms, which makes the circuit performance unable to be further optimized. In this paper, we propose a power and area optimization approach of mixed polarity RM expression （MPRM） for incompletely specified Boolean functions based on Non-Dominated Sorting Genetic Algorithm II （NSGA-II）. Firstly, the incompletely specified Boolean function is transformed into zero polarity incompletely specified MPRM （ISMPRM） by using a novel ISMPRM acquisition algorithm. Secondly, the polarity and allocation of don＇t care terms of ISMPRM is encoded as chromosome. Lastly, the Pareto optimal solutions are obtained by using NSGA-II, in which MPRM corresponding to the given chromosome is obtained by using a chromosome conversion algorithm. The results on incompletely specified Boolean functions and MCNC benchmark circuits show that a significant power and area improvement can be made compared with the existing power and area optimization approaches of RM circuits.

关键词： power and area optimization Reed-Muller （RM） circuit Pareto optimal solution don＇t care term chromosomeconversion

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