检索结果-内蒙古大学图书馆

A General-Purpose Many-Accelerator architecture Based on Dataflow Graph Clustering of Applications

Journal of computer Science & technology 2014年第2期29卷 239-246页

作者：陈鹏张磊韩银和陈云霁 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The combination of growing transistor counts and limited power budget within a silicon die leads to the utilization wall problem （a.k.a. ＂Dark Silicon＂）, that is only a small fraction of chip can run at full speed during a period of time. Designing accelerators for specific applications or algorithms is considered to be one of the most promising approaches to improving energy-efficiency. However, most current design methods for accelerators are dedicated for certain applications or algorithms, which greatly constrains their applicability. In this paper, we propose a novel general-purpose many-accelerator architecture. Our contributions are two-fold. Firstly, we propose to cluster dataflow graphs （DFGs） of hotspot basic blocks （BBs） in applications. The DFG clusters are then used for accelerators design. This is because a DFC is the largest program unit which is not specific to a certain application. We analyze 17 benchmarks in SPEC CPU 2006, acquire over 300 DFGs hotspots by using LLVM compiler tool, and divide them into 15 clusters based on graph similarity. Secondly, we introduce a function instruction set architecture （FISC） and illustrate how DFG accelerators can be integrated with a processor core and how they can be used by applications. Our results show that the proposed DFG clustering and FISC design can speed up SPEC benchmarks 6.2X on average.

关键词： dataflow graph many-accelerator clustering function instruction set architecture

来源：评论

学校读者我要写书评

暂无评论

A High-Performance and Cost-Efficient Interconnection Network for High-Density Servers

引用

Journal of computer Science & technology 2014年第2期29卷 281-292页

作者：包雯韬付斌章陈明宇张立新 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The high-density server is featured as low power, low volume, and high computational density. With the rising use of high-density servers in data-intensive and large-scale web applications, it requires a high-performance and cost-efficient intra-server interconnection network. Most of state-of-the-art high-density servers adopt the fully-connected intra-server network to attain high network performance. Unfortunately, this solution costs too much due to the high degree of nodes. In this paper, we exploit the theoretically optimized Moore graph to interconnect the chips within a server. Accounting for the suitable size of applications, a 50-size Moore graph, called Hoffman-Singleton graph, is adopted. In practice, multiple chips should be integrated onto one processor board, which means that the original graph should be partitioned into homogeneous connected subgraphs. However, the existing partition scheme does not consider above problem and thus generates heterogeneous subgraphs. To address this problem, we propose two equivalent-partition schemes for the Hoffman-Singleton graph. In addition, a logic-based and minimal routing mechanism, which is both time and area efficient, is proposed. Finally, we compare the proposed network architecture with its counterparts, namely the fully-connected, Kautz and Torus networks. The results show that our proposed network can achieve competitive performance as fully-connected network and cost close to Torus.

关键词： high-density server interconnection network Moore graph Hoffman-Singleton graph equivalent partition

来源：评论

学校读者我要写书评

暂无评论

Optimizing Parallel S_n Sweeps on Unstructured Grids for Multi-Core Clusters

引用

Journal of computer Science & technology 2013年第4期28卷 657-670页

作者：闫洁谭光明孙凝晖 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences

In particle transport simulations, radiation effects are olden described by the discrete ordinates （Sn） form of Boltzmann equation. In each ordinate direction, the solution is computed by sweeping the radiation flux across the grid. Parallel Sn sweep on an unstructured grid can be explicitly modeled as topological traversal through an equivalent directed acyclic graph （DAG）, which is a data-driven algorithm. Its traditional design using MPI model results in irregular communication of massive short messages which cannot be efficiently handled by MPI runtime. Meanwhile, in high-end HPC cluster systems, multicore has become the standard processor configuration of a single node. The traditional data-driven algorithm of Sn sweeps has not exploited potential advantages of multi-threading of multicore on shared memory. These advantages, however, as we shall demonstrate, could provide an elegant solution resolving problems in the previous MPI-only design. In this paper, we give a new design of data-driven parallel Sn sweeps using hybrid MPI and Pthread programming, namely Sweep-H, to exploit hierarchical parallelism of processes and threads. With special multi-threading techniques and vertex schedule policy, Sweep-H gets more efficient communication and better load balance. We further present an analytical performance model for Sweep-H to reveal why and when it is advantageous over former MPI counterpart. On a 64-node multicore cluster system with 12 cores per node, 768 cores in total, Sweep-H achieves nearly linear scalability for moderate problem sizes, and better absolute performance than the previous times speedup on 64 nodes）. MPI algorithm on more than 16 nodes （by up to two

关键词： parallel Sn sweep unstructured grid data-driven algorithm

来源：评论

学校读者我要写书评

暂无评论

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach

引用

Science China(Information Sciences) 2018年第11期61卷 31-47页

作者： Xiaowei LI Guihai YAN Jing YE Ying WANG State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

If your computer crashes, you can revive it by a reboot, an empirical solution that usually turns out to be effective. The rationale behind this solution is that transient faults, either in hardware or software,can be fixed by refreshing the machine state. Such a "silver bullet", however, could be futile in the future because the faults, especially those existing in the hardware such as Integrated Circuit(IC) chips, cannot be eliminated by refreshing. What we need is a more sophisticated mechanism to steer the system back to the right track. The "magic cure" is the Fault Tolerance On-Chip(FTOC) mechanism, which relies on a suite of built-in design-for-reliability logic, including fault detection, fault diagnosis, and error recovery, working in a self-supportive manner. We have exploited the FTOC to build a holistic solution ranging from on-chip fault detection to error recovery mechanisms to address faults caused by chips progressively aging. Besides fault detection, the FTOC paradigm provides attractive benefits, such as facilitating graceful performance degradation, mitigating the impact of verification blind spots, and improving the chip yield.

关键词： fault tolerance on-chip self-test self-diagnosis self-repair

来源：评论

学校读者我要写书评

暂无评论

Reinventing Memory system Design for Many-Accelerator architecture

引用

Journal of computer Science & technology 2014年第2期29卷 273-280页

作者：王颖张磊韩银和李华伟 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The many-accelerator architecture, mostly composed of general-purpose cores and accelerator-like function units （FUs）, becomes a great alternative to homogeneous chip multiprocessors （CMPs） for its superior power-efficiency. However, the emerging many-accelerator processor shows a much more complicated memory accessing pattern than general purpose processors （GPPs） because the abundant on-chip FUs tend to generate highly-concurrent memory streams with distinct locality and bandwidth demand. The disordered memory streams issued by diverse accelerators exhibit a mutual- interference behavior and cannot be efficiently handled by the orthodox main memory interface that provides an inflexible data fetching mode. Unlike the traditional DRAM memory, our proposed Aggregation Memory system （AMS） can function adaptively to the characterized memory streams from different FUs, because it provides the FUs with different data fetching sizes and protects their locality in memory access by intelligently interleaving their data to memory devices through sub-rank binding. Moreover, AMS can batch the requests without sub-rank conflict into a read burst with our optimized memory scheduling policy. Experimental results from trace-based simulation show both conspicuous performance boost and energy saving brought by AMS.

关键词： many-accelerator chip multiprocessor memory general purpose processor

来源：评论

学校读者我要写书评

暂无评论

Accelerating DNN-based 3D point cloud processing for mobile computing

引用

Science China(Information Sciences) 2019年第11期62卷 40-50页

作者： Bosheng LIU Xiaoming CHEN Yinhe HAN Jiajun LI Haobo XU Xiaowei LI State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

3D point cloud data, which are produced by various 3 D sensors such as LIDAR and stereo cameras, have been widely deployed by industry leaders such as Google, Uber, Tesla, and Mobileye, for mobile robotic applications such as autonomous driving and humanoid robots. Point cloud data, which are composed of reliable depth information, can provide accurate location and shape characteristics for scene understanding, such as object recognition and semantic segmentation. However, deep neural networks(DNNs), which directly consume point cloud data, are particularly computation-intensive because they have to not only perform multiplication-and-accumulation(MAC) operations but also search neighbors from the irregular 3 D point cloud data. Such a task goes beyond the capabilities of general-purpose processors in realtime to figure out the solution as the scales of both point cloud data and DNNs increase from application to application. We present the first accelerator architecture that dynamically configures the hardware onthe-fly to match the computation of both neighbor point search and MAC computation for point-based DNNs. To facilitate the process of neighbor point search and reduce the computation costs, a grid-based algorithm is introduced to search neighbor points from a local region of grids. Evaluation results based on the scene recognition and segmentation tasks show that the proposed design harvests 16.4× higher performance and saves 99.95% of energy than an NVIDIA Tesla K40 GPU baseline in point cloud scene understanding applications.

关键词： deep neural network acceleration point cloud data neighbor point search mobile robotics hardware architecture

来源：评论

学校读者我要写书评

暂无评论

Runtime Engine for Dynamic Profile Guided Stride Prefetching

引用

Journal of computer Science & technology 2008年第4期23卷 633-643页

作者：邹琼李晓峰章隆兵 Department of Computer Science University of Science and Technology of China Intel China Research Center Key Laboratorg of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Stride prefetching is recognized as an important technique to improve memory access performance. The prior work usually profiles and/or analyzes the program behavior offline, and uses the identified stride patterns to guide the compilation process by injecting the prefetch instructions at appropriate places. There are some researches trying to enable stride prefetching in runtime systems with online profiling, but they either cannot discover cross-procedural prefetch opportunity, or require special supports in hardware or garbage collection. In this paper, we present a prefetch engine for JVM （Java Virtual Machine）. It firstly identifies the candidate load operations during just-in-time （JIT） compilation, and then instruments the compiled code to profile the addresses of those loads. The runtime profile is collected in a trace buffer, which triggers a prefetch controller upon a protection fault. The prefetch controller analyzes the trace to discover any stride patterns, then modifies the compiled code to inject the prefetch instructions in place of the instrumentations. One of the major advantages of this engine is that, it can detect striding loads in any virtual code places for both regular and irregular code, not being limited with plain loop or procedure scopes. Actually we found the cross-procedural patterns take about 30% of all the prefetchings in the representative Java benchmarks. Another major advantage of the engine is that it has runtime overhead much smaller （the maximal is less than 4.0%） than the benefits it brings. Our evaluation with Apache Harmony JVM shows that the engine can achieve an average 6.2% speed-up with SPECJVM98 and DaCapo on Intel Pentium 4 platform, in spite of the runtime overhead.

关键词： stride prefetching dynamic profiling runtime system

来源：评论

学校读者我要写书评

暂无评论

Reliable and Energy Efficient Protocol for Wireless Sensor Network

引用

Tsinghua Science and technology 2007年第S1期12卷 95-100页

作者：阚保强蔡理徐勇军 College of Science Air Force Engineering University Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Low-power design is one of the most important issues in wireless sensor networks (WSNs) , while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make the power consumption down, but excessive interferences from potential adjacent operating links and communication reliability between nodes should be considered. In this paper, a reliable and energy efficient protocol is presented, which adopts adaptive rate control based on an optimal TP. A mathematical model considering average interference and network connectivity was used to predict the optimal TP. Then for the optimal TP, active nodes adaptively chose the data rate with the change of bit-error–rate(BER) performance. The efficiency of the new strategy was validated by mathematical analysis and simulations. Compared with 802.11 DCF which uses maximum unified TP and BASIC protocol, it is shown that the higher average throughput can achieve while the energy consumption per useful bit can be reduced according to the results.

关键词： wireless sensor networks reliable communication energy efficient optimal transmitting power adaptive link control

来源：评论

学校读者我要写书评

暂无评论

An introduction to CPU and DSP design in China

引用

Science China(Information Sciences) 2016年第1期59卷 58-65页

作者： Weiwu HU Yifu ZHANG Jie FU State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Loongson Technology Corporation Limited School of Computer and Control Engineering University of Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences

In recent years, China has witnessed considerable achievements in the production of domesticallydesigned CPUs and DSPs. Owing to fifteen years of hard work that began in 2001, significant progress has been made in Chinese domestic CPUs and DSPs, primarily represented by Loongson and Shen Wei *** parts of the CPU design techniques are comparable to the world’s most advanced designs. A special issue published in Scientia Sinica I nf ormationis in April 2015, is dedicated to exhibiting the technical advancements in Chinese domestically-designed CPUs and DSPs. The content in this issue describes the design and optimization of high performance processors and the key technologies in processor development; these include high-performance micro-architecture design, many-core and multi-core design, radiation hardening design, highperformance physical design, complex chip verification, and binary translation technology. We hope that the articles we collected will promote understanding of CPU/DSP progress in China. Moreover, we believe that the future of Chinese domestic CPU/DSP processors is quite promising.

关键词： Chinese domestic CPUs and DSPs Loongson CPU Shen Wei CPU YHFT DSP BWDSP

来源：评论

学校读者我要写书评

暂无评论

Fault Tolerance Mechanism in Chip Many-Core Processors

引用

Tsinghua Science and technology 2007年第S1期12卷 169-174页

作者：张磊韩银和李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences Beijing 100080China

As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors’ yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors’ performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.

关键词： chip many-core processors yield fault tolerance reconfiguration network-on-chip

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：