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A General-Purpose Many-Accelerator architecture Based on Dataflow Graph Clustering of Applications

Journal of computer Science & technology 2014年第2期29卷 239-246页

作者：陈鹏张磊韩银和陈云霁 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The combination of growing transistor counts and limited power budget within a silicon die leads to the utilization wall problem （a.k.a. ＂Dark Silicon＂）, that is only a small fraction of chip can run at full speed during a period of time. Designing accelerators for specific applications or algorithms is considered to be one of the most promising approaches to improving energy-efficiency. However, most current design methods for accelerators are dedicated for certain applications or algorithms, which greatly constrains their applicability. In this paper, we propose a novel general-purpose many-accelerator architecture. Our contributions are two-fold. Firstly, we propose to cluster dataflow graphs （DFGs） of hotspot basic blocks （BBs） in applications. The DFG clusters are then used for accelerators design. This is because a DFC is the largest program unit which is not specific to a certain application. We analyze 17 benchmarks in SPEC CPU 2006, acquire over 300 DFGs hotspots by using LLVM compiler tool, and divide them into 15 clusters based on graph similarity. Secondly, we introduce a function instruction set architecture （FISC） and illustrate how DFG accelerators can be integrated with a processor core and how they can be used by applications. Our results show that the proposed DFG clustering and FISC design can speed up SPEC benchmarks 6.2X on average.

关键词： dataflow graph many-accelerator clustering function instruction set architecture

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A High-Performance and Cost-Efficient Interconnection Network for High-Density Servers

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Journal of computer Science & technology 2014年第2期29卷 281-292页

作者：包雯韬付斌章陈明宇张立新 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The high-density server is featured as low power, low volume, and high computational density. With the rising use of high-density servers in data-intensive and large-scale web applications, it requires a high-performance and cost-efficient intra-server interconnection network. Most of state-of-the-art high-density servers adopt the fully-connected intra-server network to attain high network performance. Unfortunately, this solution costs too much due to the high degree of nodes. In this paper, we exploit the theoretically optimized Moore graph to interconnect the chips within a server. Accounting for the suitable size of applications, a 50-size Moore graph, called Hoffman-Singleton graph, is adopted. In practice, multiple chips should be integrated onto one processor board, which means that the original graph should be partitioned into homogeneous connected subgraphs. However, the existing partition scheme does not consider above problem and thus generates heterogeneous subgraphs. To address this problem, we propose two equivalent-partition schemes for the Hoffman-Singleton graph. In addition, a logic-based and minimal routing mechanism, which is both time and area efficient, is proposed. Finally, we compare the proposed network architecture with its counterparts, namely the fully-connected, Kautz and Torus networks. The results show that our proposed network can achieve competitive performance as fully-connected network and cost close to Torus.

关键词： high-density server interconnection network Moore graph Hoffman-Singleton graph equivalent partition

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Reinventing Memory system Design for Many-Accelerator architecture

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Journal of computer Science & technology 2014年第2期29卷 273-280页

作者：王颖张磊韩银和李华伟 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The many-accelerator architecture, mostly composed of general-purpose cores and accelerator-like function units （FUs）, becomes a great alternative to homogeneous chip multiprocessors （CMPs） for its superior power-efficiency. However, the emerging many-accelerator processor shows a much more complicated memory accessing pattern than general purpose processors （GPPs） because the abundant on-chip FUs tend to generate highly-concurrent memory streams with distinct locality and bandwidth demand. The disordered memory streams issued by diverse accelerators exhibit a mutual- interference behavior and cannot be efficiently handled by the orthodox main memory interface that provides an inflexible data fetching mode. Unlike the traditional DRAM memory, our proposed Aggregation Memory system （AMS） can function adaptively to the characterized memory streams from different FUs, because it provides the FUs with different data fetching sizes and protects their locality in memory access by intelligently interleaving their data to memory devices through sub-rank binding. Moreover, AMS can batch the requests without sub-rank conflict into a read burst with our optimized memory scheduling policy. Experimental results from trace-based simulation show both conspicuous performance boost and energy saving brought by AMS.

关键词： many-accelerator chip multiprocessor memory general purpose processor

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The 5th International Conference on Biomedical Engineering and Biotechnology (ICBEB 2016) Abstracts

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BMC MEDICAL IMAGING 2016年第SUPPL 1期16卷 65-65页

作者： [Anonymous] Department of MRI Shandong Medical Imaging Research Institute Affiliated to Shandong University Jinan Shandong 250021 People’s Republic of China Department of Interventional Radiology Shandong Provincial Hospital Affiliated to Shandong University Jinan Shandong 250021 People’s Republic of China College of Information Science and Technology Engr. Research Center of Digitized Textile & Fashion Tech. for Ministry of Education Donghua University Shanghai 201620 China Intelligent multimedia information processing Lab College of Software Northeastern University Shenyang Liaoning Province 110004 China Institute of Biomedical and Health Engineering Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Shenzhen 518055 China School of Computer Science and Technology Nanjing Normal University Nanjing China Department of Electrical Engineering The City College of New York CUNY New York USA Jiangsu Key Laboratory of 3D Printing Equipment and Manufacturing Nanjing China School of Electronic Science and Engineering Nanjing University Nanjing Jiangsu 210046 China College of Engineering Nanyang Technological University Singapore 639798 Singapore School of Electronic Information Shanghai Dianji University Shanghai China School of Natural Sciences and Mathematics Shepherd University Shepherdstown WV 25443 USA Davis College of Agriculture Natural Resources and Design West Virginia University Morgantown WV 26505 USA State Key Laboratory of Millimeter Waves Southeast University Nanjing 210096 China Center of Medical Physics and Technology Hefei Institutes of Physical Science Chinese Academy of Sciences Hefei China College of Agricultural and Life Sciences University of Florida Gainesville FL 32611 USA Courant Institute of Mathematical Sciences New York University New York NY 10012 USA Translational Imaging Division & MRI Unit Columbia University and New York State Psychiatric Institute New York NY 10032 USA Guangxi Key Laboratory of Manufacturing System & Adv

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An Elastic architecture Adaptable to Various Application Scenarios

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Journal of computer Science & technology 2014年第2期29卷 227-238页

作者：伍岳陈云霁陈天石郭崎张磊 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences IBM Research-China

The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture （EA） to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters （instruction set, branch predictor, data path, memory hierarchy, concurrency, status^zcontrol, and so on） on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP （energy-delay product） for 31.14% in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals＇ lengths and their elasticities.

关键词： architecture design configurable elasticity energy-delay product reduction

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A New Algorithm for Non-rigid Point Matching Using Geodesic Graph Model

A New Algorithm for Non-rigid Point Matching Using Geodesic ...

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IEEE International Conference on Mechatronics and Automation

作者： Deheng Qian Tianshi Chen Hong Qiao State Key Laboratory of Management and Control for Complex Systems Institute of Automation Chinese Academy of Sciences Beijing 100190 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9781479970995

Point matching is a problem of finding the optimum matching between two sets of key points which are extracted from the surfaces of objects. A popular approach represents the features of a set of points with a graph model. Traditionally, the measurement applied in the graph model is the Euclidian distance, which is not suitable for objects with non-rigid deformations. In this paper, we propose a novel graph model called the geodesic graph model (GGM) which uses a geodesic-like distance as its measurement. GGM can better tackle non-rigid deformations because the geodesic-like distance is a kind of invariant structural feature during non-rigid deformations. The building process of the GGM is justified under the assumption that all the key points are spanning on a manifold. To further handle the deviations of key point locations, we come up with a feature weighting process to increase our algorithm's robustness. We conduct several experiments on different kinds of deformations over several widely used datasets. Experimental results demonstrate the effectiveness of our algorithm.

关键词： Point matching non-rigid deformation manifold geodesic distance

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Memory Efficient Two-Pass 3D FFT Algorithm for Intel~ Xeon Phi^(TM) Coprocessor

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Journal of computer Science & technology 2014年第6期29卷 989-1002页

作者：刘益群李焱张云泉张先轶 Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences Department of Computer Science and Technology Tsinghua University CCF ACM IEEE State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences

Equipped with 512-bit wide SIMD inst d large numbers of computing cores, the emerging x86-based Intel（R） Many Integrated Core （MIC） architecture ot only high floating-point performance, but also substantial off-chip memory bandwidth. The 3D FFT （three-di fast Fourier transform） is a widely-studied algorithm; however, the conventional algorithm needs to traverse the three times. In each pass, it computes multiple 1D FFTs along one of three dimensions, giving rise to plenty of rided memory accesses. In this paper, we propose a two-pass 3D FFT algorithm, which mainly aims to reduce of explicit data transfer between the memory and the on-chip cache. The main idea is to split one dimension into ensions, and then combine the transform along each sub-dimension with one of the rest dimensions respectively erence in amount of TLB misses resulting from decomposition along different dimensions is analyzed in detail. el parallelism is leveraged on the many-core system for a high degree of parallelism and better data reuse of loc On top of this, a number of optimization techniques, such as memory padding, loop transformation and vectoriz employed in our implementation to further enhance the performance. We evaluate the algorithm on the Intel（R） PhiTM coprocessor 7110P, and achieve a maximum performance of 136 Gflops with 240 threads in offload mode, which ts the vendor-specific Intel（R）MKL library by a factor of up to 2.22X.

关键词： 3D-FFT memory efficie many-core Many Integrated Core Intel（R） Xeon PhiTM

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Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing

Enhanced LCCG: A novel test clock generation scheme for fast...

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Asia and South Pacific Design Automation Conference

作者： Songwei Pei Ye Geng Huawei Li Jun Liu Song Jin Beijing University of Chemical Technology Beijing 100029 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing CN School of Computer and Information University of Technology Hefei China School of Electrical and Electronic Engineering North China Electric Power University Baoding China

ISBN: (纸本)9781479977932

On-chip faster-than-at-speed delay testing provides a promising way for small delay defect detection. However, the frequency of on-chip generated test clock would be impacted by process variations. Hence, it requires determining the actual frequency of generated test clock to ensure the effectiveness of faster-than-at-speed delay testing. In this paper, we present a novel test clock generation scheme, namely Enhanced LCCG, for faster-than-at-speed delay testing. In the proposed scheme, faster-than-at-speed test clock is firstly generated by configuring the corresponding control information specified in the test pattern into Enhanced LCCG. Then, by constructing oscillation paths and counting the corresponding oscillation iteration numbers, the actual frequency of test clock can be measured and calculated with high resolution. Experimental results are presented to validate the proposed method.

关键词： Delays Clocks Oscillators Testing Frequency measurement Logic gates

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Intelligent test case generation based on branch and bound

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The Journal of China Universities of Posts and Telecommunications 2014年第2期21卷 91-97,103页

作者： XING Ying GONG Yun-zhan WANG Ya-wen ZHANG Xu-zhou State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications School of Electronic and Information Engineering Liaoning Technical University State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences

Path-oriented test case generation is in essence a constraint satisfaction problem （CSP） solved by search strategies, among which backtracking algorithms are widely used. In this article, the backtracking algorithm branch and bound （BB） is introduced to generate path-oriented test cases automatically. A model based on state space search is proposed to construct the search tree dynamically. The BB is optimized from two perspectives. Variable permutation with a heuristic rule to break ties is adopted for the branching operation, and interval computation with analysis on the monotony of branching conditions is utilized for the bounding operation. Empirical experiments show that the proposed method performs well with linear complexity, and reaches 100% coverage on some benchmark programs with an advantage over some static and dynamic algorithms.

关键词： test case generation constraint satisfaction problem branch and bound state space search

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Response Policies to Process Module Failure in Single-Arm Cluster Tools Subject to Wafer Residency Time Constraints

Response Policies to Process Module Failure in Single-Arm Cl...

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作者： Qiao, Yan Pan, Chun-Rong Wu, Nai-Qi Zhou, Mengchu Department of Industrial Engineering School of Electro-Mechanical Engineering Guangdong University of Technology Guangzhou510006 China School of Mechatronics and Electrical Engineering Jiangxi University of Science and Technology Ganzhou341000 China Institute of Systems Engineering Macau University of Science and Technology Taipa China Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai201804 China Department of Electrical and Computer Engineering New Jersey Institute of Technology NewarkNJ07102-1982 United States

In semiconductor manufacturing, wafer residency time constraints make the scheduling problem of cluster tools complicated. A process module (PM) in cluster tools is prone to failure. It is crucial to deal with any such failure in a proper and timely manner. If there are feasible periodic schedules in operating a cluster tool before and after a PM failure, it is desired to make it operate continuously when such a failure occurs. However, due to wafer residency time constraints, it is highly challenging to control a tool such that it can be correctly transferred from a feasible schedule before failure to another after it. To solve this problem, a Petri net model is developed to describe the dynamic behavior of a single-arm cluster tool and failure response policies are proposed. The proposed policies are formulated via simple control laws for their easy implementation. Examples are given to show them. © 2015 IEEE.

关键词： Scheduling

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