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International Conference on Networking, architecture, and Storage (NAS)

作者： Li Liu Mingyu Chen Yungang Bao Jianwei Xu Jianping Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

This paper presents a network memory architecture and makes a performance model to analysis the slowdown caused by the remote access delay. In this architecture the network memory is accessed through a smart network memory controller. A local page cache and a virtual page prefetching engine are designed in the smart network memory controller to improve the memory access performance.

关键词： Prefetching Delay Memory architecture Memory management computer architecture Engines Monitoring

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ESNet: Evolution and Succession Network for High-Resolution Salient Object Detection 41

ESNet: Evolution and Succession Network for High-Resolution ...

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41st International Conference on Machine Learning, ICML 2024

作者： Liu, Hongyu Cong, Runmin Li, Hua Xu, Qianqian Huang, Qingming Zhang, Wei Institute of Information Science Beijing Jiaotong University Beijing Key Laboratory of Advanced Information Science and Network Technology Beijing China School of Control Science and Engineering Shandong University Key Laboratory of Machine Intelligence and System Control Ministry of Education Jinan China School of Computer Science and Technology Hainan University Hainan China Key Laboratory of Intelligent Information Processing Institute of Computing Technology CAS Beijing China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China

Preserving details and avoiding high computational costs are the two main challenges for the High-Resolution Salient Object Detection (HRSOD) task. In this paper, we propose a two-stage HRSOD model from the perspective of evolution and succession, including an evolution stage with Low-resolution Location Model (LrLM) and a succession stage with High-resolution Refinement Model (HrRM). The evolution stage achieves detail-preserving salient objects localization on the low-resolution image through the evolution mechanisms on supervision and feature;the succession stage utilizes the shallow high-resolution features to complement and enhance the features inherited from the first stage in a lightweight manner and generate the final high-resolution saliency prediction. Besides, a new metric named Boundary-Detail-aware Mean Absolute Error (MAEBD) is designed to evaluate the ability to detect details in high-resolution scenes. Extensive experiments on five datasets demonstrate that our network achieves superior performance at real-time speed (49 FPS) compared to state-of-the-art methods. Our code is publicly available at: https://***/rmcong/ESNet_ICML24. Copyright 2024 by the author(s)

关键词： Miocene

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PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse of Optimizations on GPGPUs

PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Dongni Han Shixiong Xu Li Chen Lei Huang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Computer Science Department Prairie View A&M University USA

Stencil computations are core of wide range of scientific and engineering applications. A lot of efforts have been put into improving efficiency of stencil calculations on different platforms, but unfortunately it is not easy to reuse. In this paper we present a PAttern-Driven Stencil compiler-based tool and a simple tuning system to reuse those well optimized methods and codes. We also suggest extensions to OpenMP, depicting high-level data structures in order to facilitate recognition of various stencil computation patterns. The PADS allows programmers to rewrite kernel of stencils or reuse source-to-source translator outputs as optimized stencil template codes with related tuning parameters, In addition, PADS consists of a OpenMP to CUDA translator and code generator using optimized template codes. It also obtains architecture-specific parameters to tune stencils across different GPU platforms. To demonstrate our system flexibility and performance portability, we illustrate four different stencil computations, Laplacian operator with Jacobi iterative method, divergence operator, 3 dimension 25 point stencil and a 2D heat equation using ADI method with periodic boundary conditions. PADS succeeds in generating all these four stencil codes using different optimization strategies and delivers a promising performance improvement.

关键词： Pattern matching Kernel Tuning Libraries Optimization Generators

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A case study of improving at-speed testing coverage of a gigahertz microprocessor

A case study of improving at-speed testing coverage of a gig...

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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： Zichu Qi Hui Liu Xiangku Li Jun Xu Weiwu Hu Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424450909;9781424450916

For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (random access memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing X states for registers, sequential bypass of macros, clock control scheme for inter-clock domains and accurate analysis of exception paths in intra-clock domains. Functional patterns are utilized to further improve the efficiency of the at-speed testing. A novel optimal flow is presented by carefully selecting these techniques. By using the flow, 90% transition fault coverage is achieved. In addition, both the number of patterns and the test time of the transition test are decreased by 15%. The total area overhead is about a few hundreds of AND cells and has little timing impact on the critical paths.

关键词： Microprocessors Clocks Test pattern generators system testing Costs Timing Automatic test pattern generation Delay Pattern analysis Laboratories

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RSAK: Random stream attack for phase change memory in video applications

RSAK: Random stream attack for phase change memory in video ...

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VLSI Test Symposium

作者： Yuntan Fang Huawei Li Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

As an emerging non-volatile memory technology, phase change memory (PCM) is promising as an alternative for traditional memories such as DRAM. In spite of its non-volatility, high density, low standby power, and resilience to soft errors, PCM has a limited write endurance or lifetime, which means that each PCM cell can only be overwritten finite times. More importantly, limited lifetime potentially provides malicious attackers an opportunity to intentionally aggravate write traffic into PCM. In this paper, from the standpoint of attackers, we propose random stream attacks (RSAK) methods for phase change memory used in video applications. Experimental results show that compared to natural video sequences, RSAK incurs higher total write traffic or worsened lifetime. RSAK also gives hints on how to build a more secure PCM in video applications to counter malicious write streams.

关键词： Phase change materials Video sequences Streaming media Random access memory Security Encoding Measurement

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Libvmi: A Library for Bridging the Semantic Gap between Guest OS and VMM

Libvmi: A Library for Bridging the Semantic Gap between Gues...

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International Conference on computer and Information technology (CIT)

作者： Haiquan Xiong Zhiyong Liu Weizhi Xu Shuai Jiao State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Semantic gap is one of the most important problems in the virtualized computer systems. Solving this problem not only helps to develop security and virtual machine monitoring applications, but also benefits for VMM resource management and VMM-based service implementation. In this paper, we first review the general architecture of virtual computer systems, especially the interaction principles between Guest OS and VMM so as to better understand the causes of semantic gap. Then we consider how to build a library that can integrate the commonalities existing in different VMMs and Guest OSes. It should be general enough to facilitate the above mentioned applications development. In order to more clearly illustrate this issue, we select Libvmi as the case study, elaborating its design philosophy and implementation. Finally, we describe how to use Libvmi with two application examples and verify its correctness and effectiveness.

关键词： Libraries Virtual machining Semantics Virtual machine monitors computer architecture Hardware computers

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Optimizing TCP loss recovery performance over mobile data networks

arXiv

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arXiv 2018年

作者： Liu, Ke Zha, Zhongbin Wan, Wenkai Aggarwal, Vaneet Fu, Binzhang Chen, Mingyu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Purdue University

Recent advances in high-speed mobile networks have revealed new bottlenecks in ubiquitous TCP protocol deployed in the Internet. In addition to differentiating non-congestive loss from congestive loss, our experiments revealed two significant performance bottlenecks during the loss recovery phase: flow control bottleneck and application stall, resulting in degradation in QoS performance. To tackle these two problems we firstly develop a novel opportunistic retransmission algorithm to eliminate the flow control bottleneck, which enables TCP sender to transmit new packets even if receiver's receiving window is exhausted. Secondly, application stall can be significantly alleviated by carefully monitoring and tuning the TCP sending buffer growth mechanism. We implemented and modularized the proposed algorithms in the Linux kernel thus they can plug-and-play with the existing TCP loss recovery algorithms easily. Using emulated experiments we showed that, compared to the existing TCP loss recovery algorithms, the proposed optimization algorithms improve the bandwidth efficiency by up to 133% and completely mitigate RTT spikes, i.e., over 50% RTT reduction, over the loss recovery phase. Copyright © 2018, The Authors. All rights reserved.

关键词： Transmission control protocol

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A novel abstraction-guided simulation approach using posterior probabilities for verification

A novel abstraction-guided simulation approach using posteri...

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International Symposium on VLSI Design, Automation and Test

作者： Jian Wang Huawei Li Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

This paper presents a novel abstraction-guided simulation approach for multiple target states which uses posterior probabilities of the states from the abstract model, instead of abstract distances used by former abstraction-guided approaches, as the guidance of simulation. The posterior probabilities carry more precise information of the abstract model, being able to offer more effective guidance as well as allow the simulation to deal with multiple target states at a time. Experimental results show that the simulation using posterior probabilities as guidance is much more efficient than that using the abstract distances, and the multiple target states simulation framework reduces the simulation cycles effectively.

关键词： Abstracts Latches Vectors Data models Concrete Engines Markov processes

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Cross-layer optimized placement and routing for FPGA soft error mitigation

Cross-layer optimized placement and routing for FPGA soft er...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Keheng Huang Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. Our analysis shows that the statistical variation of the application level factor is significant. Hence in this work, we first propose a cube-based analysis to efficiently and accurately evaluate the application level factor. And then we propose a cross-layer optimized placement and routing algorithm to reduce the SER by incorporating the application level and the physical level factor together. Experimental results show that, the average difference of the application level factor between our cube-based method and Monte Carlo golden simulation is less than 0.01. Moreover, compared with the baseline VPR placement and routing technique, the cross-layer optimized placement and routing algorithm can reduce the SER by 14% with no area and performance overhead.

关键词： Routing Wires Circuit faults Field programmable gate arrays Monte Carlo methods Algorithm design and analysis Accuracy

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SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase C...

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Asian Test Symposium (ATS)

作者： Yuntan Fang Huawei Li Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Modern video applications such as video codecs are memory-intensive. As an emerging non-volatile memory technology, phase change memory (PCM) will benefit video applications due to its high density, low leakage power and superior scalability. However, PCM consumes high write energy and can only sustain a limited write number. Hence it is necessary to reduce the write number of PCM for video applications. In this paper, we propose SoftPCM to enhance both energy efficiency and lifetime of PCM. SoftPCM utilizes the error tolerance characteristic of video applications to relax the accuracy of write operations. Experimental results show that SoftPCM can reduce 22% writes and thus improve energy efficiency and lifetime of PCM with slight video quality degradation.

关键词： Phase change materials Video recording Quality assessment Random access memory Hardware Approximation methods Reflective binary codes

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