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检索条件"机构=Key Laboratory of Computer System and Architecture Institute of Computing Technology"

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Statistical SDFC: A metric for evaluating test quality of small delay faults

Statistical SDFC: A metric for evaluating test quality of sm...

引用

International Symposium on VLSI Design, Automation and Test

作者： Xuefeng Zhu Huawei Li Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781457720802

As the technology node continues to shrink, an effective and accurate metric is essential to measure the test quality of small delay faults (SDFs), which may cause failure at circuit outputs. Owing to including gross delay fault (GDF) coverage, prior metrics cannot concentrate on the detection of SDFs. We propose a new metric, statistical SDF Coverage (S-SDFC), for differentiating SDFs and GDFs and evaluating the test quality of SDFs under the statistical delay quality model. Experimental results show that S-SDFC is more conservative and effective in evaluating the quality of test sets in detecting SDFs and outperforms other metrics in guiding test generation.

关键词： Circuit faults Delay Automatic test pattern generation Clocks Integrated circuit modeling

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DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only) 16

DCPUF: Placement and Routing Constraint based Dynamically Co...

引用

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

作者： Jing Ye Yu Hu Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450338561

With the development of Integrated Circuit (IC), it is a growing trend that the CPU and the FPGA are integrated into one chip. To improve the security of CPU+FPGA IC, we explore the reconfigurable feature of FPGA to implement a novel Dynamically Configured Physical Unclonable Function (DCPUF). PUF is a hardware security primitive that utilizes unpredictable process variations to produce particular challenge-response pairs, so even the chips with the same design would produce different responses for the same challenge. In the DCPUF, the FPGA configuration bits, which are specifically designed with dedicated placement and routing constraint, constitute the challenge. When a challenge is input to a CPU+FPGA IC, the CPU uses it to configure or partially configure the FPGA, and then waits for the FPGA to reply a response. In comparison with existing PUFs, the DCPUF has three major advantages: (1) different from existing PUFs with fixed designs, the logic of DCPUF is dynamically configured for each challenge, i.e. the circuits for producing different responses are different, leading to higher security; (2) much more electronic parameters affected by process variation are leveraged to make DCPUF more robust against attacks; (3) for CPU+FPGA IC, no extra hardware is needed. The experiments on real CPU+FPGA ICs show the proposed DCPUF keeps good randomness and stability.

关键词： cpu+fpga ic reconfiguration placement and routing constraint puf

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Reducing Redundancy in Data Organization and Arithmetic Calculation for Stencil Computations

Reducing Redundancy in Data Organization and Arithmetic Calc...

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Supercomputing Conference

作者： Kun Li Liang Yuan Yunquan Zhang Yue Yue State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Scienceslice Beijing China

ISBN: (数字)9781450384421

ISBN: (纸本)9781665483902

Stencil computation is one of the most important kernels in various scientific and engineering applications. A variety of work has focused on vectorization techniques, aiming at exploiting the in-core data parallelism. However, they either incur spatial data conflicts or hurt the data locality when integrated with tiling. In this paper, a novel spatial computation folding is devised to reduce the data reorganization overhead for vectorization and preserve the data locality for tiling in the data space simultaneously. We then propose an approach of temporal computation folding enhanced with shifts reusing, tessellate tiling, and semi-automatic code generation. It aims to further reduce the redundancy of arithmetic calculations and exploit the register reuse along the time dimension. Experimental results on the AVX2 and AVX-512 CPUs show that our approach obtains significant performance improvements compared with state-of-the-art techniques.

关键词： Codes High performance computing Redundancy Organizations Parallel processing Spatial databases Computational efficiency

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Robust test generation for power supply noise induced path delay faults

Robust test generation for power supply noise induced path d...

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Asia and South Pacific Design Automation Conference

作者： Xiang Fu Huawei Li Yu Hu Xiaowei Li Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

ISBN: (纸本)9781424419210

In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS'89 circuits showed test generation can be finished in a few seconds.

关键词： Noise robustness Power generation Power supplies Noise generators Delay Circuit testing Circuit faults Timing Switches Feeds

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Data Management: The Spirit to Pursuit Peak Performance on Many-Core Processor

Data Management: The Spirit to Pursuit Peak Performance on M...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Yongbin Zhou Junchao Zhang Shuai Zhang Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

To date, most of many-core prototypes employ tiled topologies connected through on-chip networks. The throughput and latency of the on-chip networks usually become to the bottleneck to achieve peak performance especially for communication intensive applications. Most of studies are focus on on-chip networks only, such as routing algorithms or router micro-architecture, to improve the above metrics. The salient aspect of our approach is that we provide a data management framework to implement high efficient on-chip traffic based on overall many-core system. The major contributions of this paper include that: (1) providing a novel tiled many-core architecture which supports software controlled on-chip data storage and movement management; (2) identifying that the asynchronous bulk data transfer mechanism is an effective method to tolerant the latency of 2-D mesh on-chip networks. At last, we evaluate the 1-D FFT algorithm on the framework and the performance achieves 47.6 Gflops with 24.8% computation efficiency.

关键词： Network-on-a-chip Delay Prototypes Network topology Throughput Routing system-on-a-chip Communication system traffic control computer architecture Memory

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Battery discharge characteristics of wireless sensors in building applications

Battery discharge characteristics of wireless sensors in bui...

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2012 9th IEEE International Conference on Networking, Sensing and Control, ICNSC 2012

作者： Guo, Wenqi Healy, William M. Zhou, MengChu Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102 United States National Institute of Standards and Technology Gaithersburg MD 20899 United States Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 200092 China

ISBN: (纸本)9781467303880

Sensor nodes in wireless networks often use batteries as their source of energy, but replacing or recharging exhausted batteries in a deployed network can be difficult and costly. Therefore, prolonging battery life becomes a principal objective in the design of wireless sensor networks (WSNs). There is little published data that quantitatively analyze a sensor node's lifetime under different operating conditions. This paper presents several experiments to quantify the impact of key wireless sensor network design and environmental parameters on battery performance. Our testbed consists of MicaZ motes, commercial alkaline batteries, and a suite of techniques for measuring battery performance. We evaluate known parameters, such as communication distance, working channel and operating power that play key roles in battery performance. Through extensive real battery discharge measurements, we expect our results to serve as a quantitative basis for future research in designing and implementing battery-efficient sensing applications and protocols. © 2012 IEEE.

关键词： Zigbee

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Static Crosstalk Noise Analysis with Transition Map

Static Crosstalk Noise Analysis with Transition Map

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Minjin Zhang Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

As the feature size scales into the nanometer era, crosstalk noise begins to exert a more significant adverse influence on circuit and need to be estimated efficiently in the design process. This paper proposes a novel static crosstalk noise analysis method to quickly and accurately calculate the propagation and combination of glitch noise in circuit. The key of this approach, namely transition map, is a bitmap structure which records the possible arrival times of a line. Based on it, this approach can cope with multiple coupling effects using the timing information of circuit. The analytical results for seven largest ISCAS89 benchmark circuits show that the proposed technique is highly effective in reducing the number of reported false noise violations.

关键词： Crosstalk Circuit noise Timing Noise reduction Noise figure Phase noise Information analysis Electronic equipment testing Circuit testing system testing

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A Synchronization-Based Alternative to Directory Protocol

A Synchronization-Based Alternative to Directory Protocol

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： He Huang Lei Liu Nan Yuan Wei Lin Fenglong Song Junchao Zhang Dongrui Fan Institute of Computing Technology Key Laboratory of Computer Systems and Architecture Chinese Academy and Sciences Beijing China

The efficient support of cache coherence is extremely important to design and implement many-core processors. In this paper, we propose a synchronization-based coherence (SBC) protocol to efficiently support cache coherence for shared memory many-core architectures. The unique feature of our scheme is that it doesnpsilat use directory at all. Inspired by scope consistency memory model, our protocol maintains coherence at synchronization point. Within critical section, processor cores record write-sets (which lines have been written in critical section) with bloom-filter function. When the core releases the lock, the write-set is transferred to a synchronization manager. When another core acquires the same lock, it gets the write-set from the synchronization manager and invalidates stale data in its local cache. Experimental results show that the SBC outperforms by averages of 5% in execution time across a suite of scientific applications. At the mean time, the SBC is more cost-effective comparing to directory-based protocol that requires large amount of hardware resource and huge design verification effort.

关键词： Protocols Coherence Distributed processing Application software Helium Laboratories Concurrent computing Distributed computing computer architecture Memory architecture

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How Does Updatable Learned Index Perform on Non-Volatile Main Memory?

How Does Updatable Learned Index Perform on Non-Volatile Mai...

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International Conference on Data Engineering Workshops

作者： Leying Chen Shimin Chen State Key Laboratory of Computer Architecture Institute of Computing Technology CAS University of Chinese Academy of Sciences

Recent work on learned index opens a new research direction for index structures. By exploiting the data distribution, a read-only learned index can achieve much better time and space performance than B+-Trees. A number of recent studies propose enhanced learned index structures that provide various levels of support for insertions and deletions. Among them, ALEX, an updatable adaptive learned index, provides the most comprehensive support, allowing on-the-fly insertions and dynamically adjusting the index structure similar to the B+-Tree. In this paper, we study learned index from a new perspective, trying to understand how ALEX performs on Non-Volatile Main Memory (NVM). We analyze the insertion behaviors of ALEX and experimentally evaluate its performance on a real machine equipped with Intel Optane DC Persistent Memory. We find that learning data distributions in learned index makes it feasible to create very large leaf nodes, and reduce the tree height drastically for better search performance. However, this design choice causes a large number of NVM writes for insertion operations, even for the well optimized ALEX design.

关键词： Nonvolatile memory Conferences Vegetation Data engineering Indexes

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BigDataBench: A big data benchmark suite from internet services

BigDataBench: A big data benchmark suite from internet servi...

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20th IEEE International Symposium on High Performance computer architecture, HPCA 2014

作者： Wang, Lei Zhan, Jianfeng Luo, Chunjie Zhu, Yuqing Yang, Qiang He, Yongqiang Gao, Wanling Jia, Zhen Shi, Yingjie Zhang, Shujie Zheng, Chen Lu, Gang Zhan, Kent Li, Xiaona Qiu, Bizhu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Dropbox United States Huawei China Tencent China Baidu China Yahoo United States University of Chinese Academy of Sciences China

ISBN: (纸本)9781479930975

As architecture, systems, and data management communities pay greater attention to innovative big data systems and architecture, the pressure of benchmarking and evaluating these systems rises. However, the complexity, diversity, frequently changed workloads, and rapid evolution of big data systems raise great challenges in big data benchmarking. Considering the broad use of big data systems, for the sake of fairness, big data benchmarks must include diversity of data and workloads, which is the prerequisite for evaluating big data systems and architecture. Most of the state-of-the-art big data benchmarking efforts target evaluating specific types of applications or system software stacks, and hence they are not qualified for serving the purposes mentioned above. © 2014 IEEE.

关键词： Big data

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