检索结果-内蒙古大学图书馆

International Conference on Grid and Cooperative computing Workshops (GCCW)

作者： Lei Xie Hongsong Zhu Yongjun Xu Yuefei Zhu Institute of Information Engineering Information and Engineering University Zhengzhou China Advanced Test Technology Laboratory Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Wireless sensor network (WSN), which is integrated with many technologies such as sensor, embedded computing, wireless communication and distributed information processing etc., is becoming an important branch of ubiquitous computing research. WSN is composed of a large number of distributed sensor nodes, so to ensure the sensor nodes dependable is essential to security of whole network. By introducing a lightweight tamper-resistance design based on security co-processor into sensor nodes, this paper loosens up the security assumptions of WSN, and redefines the objectives of WSN security. Based on such secure infrastructure, the paper also proposes a concise and effective key pre-distribution scheme, in which each node needs to send only one cluster key announcement message and cluster key net can be set up within neighborhood

关键词： Wireless sensor networks Pervasive computing Ubiquitous computing Information security computer networks computer architecture Sensor arrays Design engineering Laboratories Embedded computing

来源：评论

学校读者我要写书评

暂无评论

Imperceptible and Sparse Adversarial Attacks via a Dual-Population-Based Constrained Evolutionary Algorithm

IEEE Transactions on Artificial Intelligence

引用

IEEE Transactions on Artificial Intelligence 2023年第2期4卷 268-281页

作者： Tian, Ye Pan, Jingwen Yang, Shangshang Zhang, Xingyi He, Shuping Jin, Yaochu Anhui University Key Laboratory of Intelligent Computing and Signal Processing of Ministry of Education Institutes of Physical Science and Information Technology Hefei230601 China Hefei Comprehensive National Science Center Institute of Artificial Intelligence Hefei230088 China Anhui University School of Computer Science and Technology Hefei230601 China Anhui University Key Laboratory of Intelligent Computing and Signal Processing of Ministry of Education School of Artificial Intelligence Hefei230601 China Anhui University Anhui Engineering Laboratory of Human-Robot Integration System and Intelligent Equipment School of Electrical Engineering and Automation Hefei230601 China Bielefeld University Faculty of Technology Bielefeld33619 Germany

The sparse adversarial attack has attracted increasing attention due to the merit of a low attack cost via changing a small number of pixels. However, the generated adversarial examples are easily detected in vision since the perturbation to each pixel is relatively large. To achieve imperceptible and sparse adversarial attacks, this article formulates a bi-objective constrained optimization problem, simultaneously minimizing the 0 and 2 distances to the original image, and proposes a dual-population-based constrained evolutionary algorithm to solve it. The proposed method solves the optimization problem by evolving two populations, where one population is responsible for finding feasible solutions (i.e., successful attacks) and the other one is to minimize both the 0 and 2 distances. Moreover, a population initialization strategy and two genetic operators are customized to accelerate the convergence speed. Experimental results indicate that the proposed method can achieve high success rates with low attack costs, and strikes a better balance between the 0 and 2 distances than state-of-the-art methods. © 2020 IEEE.

关键词： Evolutionary algorithms

来源：评论

学校读者我要写书评

暂无评论

Predoop: Preempting reduce task for job execution accelerations

Lecture Notes in Computer Science (including subseries Lectu...

引用

Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2014年 8807卷 167-180页

作者： Liang, Yi Wang, Yufeng Fan, Minglu Zhang, Chen Zhu, Yuqing Department of Computer Science Beijing University of Technology Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy Sciences Beijing China

ISBN: (纸本)9783319130200

Map/Reduce is a popular parallel processing framework for data intensive computing. For overlapping the Map task’s execution phase and the Reduce task’s intermediate data fetching and merging phase, existing Map/Reduce schedulers always pre-launch the Reduce task at the specific threshold where its map tasks have been launched, and this pattern incurs the occupation of the consuming resources of the reduce task during its idle time on waiting for fetching the intermediate data from map tasks. To address this issue, we propose an extension version of Hadoop map/reduce framework, called Predoop, in this paper. The basic idea of Predoop is to preempt the reduce task during its idle time and allocate the released resource to the map tasks on schedule. To achieve this goal, first, we introduce the preemptive mechanism for reduce tasks and map tasks respectively to enable Map/Reduce tasks to be preempted or resumed with correct status;second, we adopt the preempting-resuming model for the reduce task with the consideration of the progress of Reduce task data fetching & merging and the Map task execution so as to determine the timing of Reduce task preemption and resuming;third, we introduce the preemption-aware task scheduling strategy to allocate the released resources to the on-schedule Map tasks with the consideration of data locality. Experimental result demonstrates that Predoop outperforms Hadoop on various workload and the average job turnaround time can be reduced by maximum of 66.57%. © Springer International Publishing Switzerland 2014.

关键词： Multitasking

来源：评论

学校读者我要写书评

暂无评论

Modeling the Impact of DVFS on Performance of Applications in Datacenter

引用

Ruan Jian Xue Bao/Journal of Software 2017年第4期28卷 845-859页

作者： Li, Deng-Hui Zhao, Jia-Cheng Cui, Hui-Min Feng, Xiao-Bing State Key Laboratory of Computer Architecture Institute of Computing Technology The Chinese Academy of Sciences Beijing100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing100049 China

Datacenters are built to house massive internet services at an affordable price. Both Op-ex (long-time operational expenditure) and Cap-ex (one-time construction costs) are directly impacted by datacenter power consumption. Thus, DVFS (dynamic voltage and frequency scaling) is widely adopted to improve per node energy efficiency. However, it is well known but has not yet been fully explored that such schemes affect an application's power consumption and performance simultaneously. This paper focuses on the impact of DVFS on performance of an application and proposes an analytical model to quantitatively characterize the relationship between an application's performance and a processor's frequency, which can be leveraged to predict the performance of an application at any frequency. Specifically, according to different memory subsystem resources accessed, instructions of an application are divided into two parts: on-chip instructions and off-chip instructions, which can be modeled independently. On-Chip instructions refer to instructions which only access on-chip resources, and their execution time is frequency-relevant and can be modeled using a linear function. Off-chip instructions stand for instructions accessing the main memory, and their execution time is dominated by memory access latency and is frequency-irrelevant. By the division and modeling of the two parts, a quantitative model can be obtained between the execution time of an application and frequency of a processor. Evaluations using two different platforms and all benchmarks of SPEC 2006 show that the derived models are very precise, with average prediction error less than 1.34%. © Copyright 2017, institute of Software, the Chinese Academy of Sciences. All rights reserved.

关键词： Energy efficiency

来源：评论

学校读者我要写书评

暂无评论

Providing fairness on shared-memory multiprocessors via process scheduling 12

Providing fairness on shared-memory multiprocessors via proc...

引用

12th Joint International Conference on Measurement and Modeling of computer systems, ACM SIGMETRICS/Performance 2012

作者： Xu, Di Wu, Chenggang Yew, Pen-Chung Li, Jianjun Wang, Zhenjiang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University Chinese Academy of Sciences Beijing China Department of Computer Science and Engineering University of Minnesota at Twin-Cities MN United States Institute of Information Science Academia Sinica Taiwan

ISBN: (纸本)9781450310970

Competition for shared memory resources on multiprocessors is the most dominant cause for slowing down applications and makes their performance varies unpredictably. It exacerbates the need for Quality of Service (QoS) on such systems. In this paper, we propose a fair-progress process scheduling (FPS) policy to improve system fairness. Its strategy is to force the equally-weighted applications to have the same amount of slowdown when they run concurrently. The basic approach is to monitor the progress of all applications at runtime. When we find an application suffered more slowdown and accumulated less effective work than others, we allocate more CPU time to give it a better parity. Our policy also allows different weights to different threads, and provides an effective and robust tuner that allows the OS to freely make tradeoffs between system fairness and higher throughput. Evaluation results show that FPS can significantly improve system fairness by an average of 53.5% and 65.0% on a 4-core processor with a private cache and a 4-core processor with a shared cache, respectively. The penalty is about 1.1% and 1.6% of the system throughput. For memory-intensive workloads, FPS also improves system fairness by an average of 45.2% and 21.1% on 4-core and 8-core system respectively at the expense of a throughput loss of about 2%. © 2012 ACM.

关键词： Throughput

来源：评论

学校读者我要写书评

暂无评论

Multiple-combinational-channel: A network architecture for workload balance and deadlock free

Multiple-combinational-channel: A network architecture for w...

引用

作者： Chen, Liwei Wang, Yipeng Wang, Huandong Wang, Wenxiang Jing, Hua Zhang, Guangfei Institute of Information Engineering Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Loongson Technology Corporation Limited Beijing China Shannon Laboratory Huawei Technologies Co. Beijing China

As the number of cores in chip multiprocessors (CMPs) increases rapidly, network-on-chips (NoCs) have become the major role in ensuring performance and power scalability. In this paper, we propose multiple-combinational-channel (MCC), a load balancing and deadlock free interconnect network, for cache-coherent non-uniform memory accessing (CC-NUMA). In order to make load more balancing and reduce power dissipation, we combine low usage channels and make high usage channels independent and wide enough, since messages transmitted over NoC have different widths and injection rates. Furthermore, based on the in-depth analysis of network traffic, we summarize four traffic patterns and establish several rules to avoid protocol-level deadlocks. We implement MCC on a 16-core CMPs, and evaluate the workload balance, area, power and performance using universal workloads. The experimental results show that MCC reduces nearly 21% power than multiple-physical-channel with similar throughput. Moreover, MCC improves 10% performance with similar area and power, compared to packet-switching architecture with virtual channels. © 2015 Elsevier B.V.

关键词： Network-on-chip

来源：评论

学校读者我要写书评

暂无评论

LazyGraph: Lazy Data Coherency for Replicas in Distributed Graph-Parallel Computation

引用

ACM SIGPLAN Notices 2018年第1期53卷 276-289页

作者： Wang, Lei Zhuang, Liangji Chen, Junhang Cui, Huimin Lv, Fang Liu, Ying Feng, Xiaobing State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9781450349116

Replicas 1 of a vertex play an important role in existing distributed graph processing systems which make a single vertex to be parallel processed by multiple machines and access remote neighbors locally without any remote access. However, replicas of vertices introduce data coherency problem. Existing distributed graph systems treat replicas of a vertex v as an atomic and indivisible vertex, and use an eager data coherency approach to guarantee replicas atomicity. In eager data coherency approach, any changes to vertex data must be immediately communicated to all replicas of v, thus leading to frequent global synchronizations and communications. In this paper, we propose a lazy data coherency approach, called LazyAsync, which treats replicas of a vertex as independent vertices and maintains the data coherency by computations, rather than communications in existing eager approach. Our approach automatically selects some data coherency points from the graph algorithm, and maintains all replicas to share the same global view only at such points, which means the replicas are enabled to maintain different local views between any two adjacent data coherency points. Based on PowerGraph, we develop a distributed graph processing system LazyGraph to implement the LazyAsync approach and exploit graph-aware optimizations. On a 48-node EC2-like cluster, LazyGraph outperforms PowerGraph on four widely used graph algorithms across a variety of real-world graphs, with a speedup ranging from 1.25x to 10.69x. © 2018 ACM.

关键词： Graph theory

来源：评论

学校读者我要写书评

暂无评论

High-performance genomic analysis framework with in-memory computing

引用

ACM SIGPLAN Notices 2018年第1期53卷 317-328页

作者： Li, Xueqi Tan, Guangming Wang, Bingchen Sun, Ninghui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9781450349116

In this paper, we propose an in-memory computing framework (called GPF) that provides a set of genomic formats, APIs and a fast genomic engine for large-scale genomic data processing. Our GPF comprises two main components: (1) scalable genomic data formats and API. (2) an advanced execution engine that supports efficient compression of genomic data and eliminates redundancies in the execution engine of our GPF. We further present both system and algorithm-specific implementations for users to build genomic analysis pipeline without any acquaintance of Spark parallel programming. To test the performance of GPF, we built a WGS pipeline on top of our GPF as a test case. Our experimental data indicate that GPF completes Whole-Genome-Sequencing (WGS) analysis of 146.9G bases Human Platinum Genome in running time of 24 minutes, with over 50% parallel efficiency when used on 2048 CPU cores. Together, our GPF framework provides a fast and general engine for large-scale genomic data processing which supports in-memory computing. © 2018 ACM.

关键词： Pipelines

来源：评论

学校读者我要写书评

暂无评论

SelectCast: Scalable data aggregation scheme in wireless sensor networks

SelectCast: Scalable data aggregation scheme in wireless sen...

引用

IEEE INFOCOM 2011

作者： Wang, Cheng Tang, Shaojie Li, Xiang-Yang Jiang, Changjun Department of Computer Science Tongji University Shanghai China Key Laboratory of Embedded System and Service Computing Ministry of Education Shanghai China Department of Computer Science Illinois Institute of Technology Chicago IL 60616 United States TNLIST School of Software Tsinghua University China

ISBN: (纸本)9781424499212

In this work, for a wireless sensor network (WSN) of n randomly placed sensors with node density λ ∈ [1, n], we study the tradeoffs between the aggregation throughput and gathering efficiency. The gathering efficiency refers to the ratio of the number of the sensors whose data have been gathered to the total number of sensors. Specifically, we design two efficient aggregation schemes, called single-hop-length (SLH) scheme and multiple-hop-length (MLH) scheme. By novelly integrating these two schemes, we theoretically prove that our protocol achieves the optimal tradeoffs, and derive the optimal aggregation throughput depending on a given threshold value (lower bound) on gathering efficiency. Particularly, we show that under the MLH scheme, for a practically important set of symmetric functions called perfectly compressible functions, including the mean, max, or various kinds of indicator functions, etc., the data from Θ(n) sensors can be aggregated to the sink at the throughput of a constant order Θ(1), implying that our MLH scheme is indeed scalable. © 2011 IEEE.

关键词： Efficiency

来源：评论

学校读者我要写书评

暂无评论

Data motifs: A lens towards fully understanding big data and ai workloads

arXiv

引用

arXiv 2018年

作者： Gao, Wanling Zhan, Jianfeng Wang, Lei Luo, Chunjie Zheng, Daoyi Tang, Fei Xie, Biwei Zheng, Chen Wen, Xu He, Xiwen Ye, Hainan Ren, Rui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing Academy of Frontier Sciences and Technology

The complexity and diversity of big data and AI workloads make understanding them difficult and challenging. This paper proposes a new approach to modelling and characterizing big data and AI workloads. We consider each big data and AI workload as a pipeline of one or more classes of units of computation performed on different initial or intermediate data inputs. Each class of unit of computation captures the common requirements while being reasonably divorced from individual implementations, and hence we call it a data motif. For the first time, among a wide variety of big data and AI workloads, we identify eight data motifs that take up most of the run time of those workloads, including Matrix, Sampling, Logic, Transform, Set, Graph, Sort and Statistic. We implement the eight data motifs on different software stacks as the micro benchmarks of an open-source big data and AI benchmark suite — BigDataBench 4.0 (publicly available from http://***/BigDataBench), and perform comprehensive characterization of those data motifs from perspective of data sizes, types, sources, and patterns as a lens towards fully understanding big data and AI workloads. We believe the eight data motifs are promising abstractions and tools for not only big data and AI benchmarking, but also domain-specific hardware and software co-design. Copyright © 2018, The Authors. All rights reserved.

关键词： Big data

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：