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17th International Conference on Extending Database technology, EDBT 2014

作者： Cao, Zhao Chen, Shimin Ma, Dongzhe Feng, Jianhua Wang, Min IBM Research Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Tsinghua University Beijing China Google Research Mountain ViewCA United States

ISBN: (纸本)9783893180653

A popular programming paradigm in the cloud, MapReduce is extensively considered and used for "big data" analysis. Unfortunately, a great many "big data" applications require capabilities beyond those originally intended by MapReduce, often burdening developers to write unnatural non-obvious MapReduce programs so as to twist the underlying system to meet the requirements. In this paper, we focus on a class of "big data" applications that in addition to MapReduce's main data source, require selective access to one or many data sources, e.g., various kinds of indices, knowledge bases, external cloud services. We propose to extend MapReduce with EFind, an Efficient and Flexible index access solution, to better support this class of applications. EFind introduces a standard index access interface to MapReduce so that (i) developers can easily and flexibly express index access operations without unnatural code, and (ii) the EFind enhanced MapReduce system can automatically optimize the index access operations. We propose and analyze a number of index access strategies that utilize caching, re-partitioning, and index locality to reduce redundant index accesses. EFind collects index statistics and performs cost-based adaptive optimization to improve index access efficiency. Our experimental results, using both realworld and synthetic data sets, show that EFind chooses execution plans that are optimal or close to optimal, and achieves a factor of 2x-8x improvements compared to an approach that accesses indices without optimization.

关键词： MapReduce

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Monitor-based Liveness-enforcing Petri Net Supervisors for Flexible Manufacturing systems 33

Monitor-based Liveness-enforcing Petri Net Supervisors for F...

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第三十三届中国控制会议

作者： YOU Dan WANG Shouguang ZHOU MengChu WU Wenhui School of Information & Electronic Engineering Zhejiang Gongshang University IEEE State Key Laboratory for Manufacturing Systems Engineering Xi’ an Jiaotong University The Key Laboratory of Embedded System and Service Computing Ministry of EducationTongji University Department of Electrical and Computer Engineering New Jersey Institute of TechnologyNewarkNJ 07102USA

ISBN: (纸本)9781479947249

Deadlocks are a rather undesirable phenomenon in flexible manufacturing systems(FMSs).This work,by adding monitors,develops a deadlock prevention policy for FMSs that can be modeled by a class of Petri nets called-S3 PR ***,an algorithm is given to reduce an S3 PR via *** on it,-resources in-S3 PRs are classified into A--resources and ***,for an-S3 PR with only B--resources,it is proved that a maximally permissive liveness-enforcing supervisor can be designed by M-controlling all the emptied strict minimal siphons(SMSs).For an-S3 PR containing A--resources,a liveness-enforcing supervisor can be designed by iteratively reducing the net via A--resources and adding the corresponding ***,a comprehensive deadlock prevention algorithm for-S3 PRs is *** FMS example is used to illustrate its application.

关键词： Flexible manufacturing system(FMS),Petri nets,deadlock prevention policy,supervisory control

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Dynamically tolerating and detecting asymmetric races

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2014年第8期51卷 1748-1763页

作者： Wang, Wenwen Wu, Chenggang Ratanaworabhan, Paruj Yuan, Xiang Wang, Zhenjiang Li, Jianjun Feng, Xiaobing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China University of Chinese Academy of Sciences Beijing100049 China Faculty of Engineering Kasetsart University Bangkok10900 Thailand

Asymmetric races are a common type of data races. They are triggered when a thread accesses a shared variable in a critical section, and another thread accesses the same shared variable not in any critical section, or in a critical section guarded by a different lock. Asymmetric races in multi-threaded programs are usually harmful. To solve the problem introduced by asymmetric races, ARace is proposed. ARace utilizes shared variable protecting and write buffer to dynamically tolerate and detect asymmetric races. Shared variable protecting is used to protect shared variables that are read-only and read-before-write in critical sections, and these shared variables should not be modified out of critical sections;write buffer is used to buffer the writing operations to shared variables in critical sections. ARace can not only tolerate asymmetric races triggered by shared variable accesses in and out of critical sections, but also detect asymmetric races triggered by shared variable accesses in concurrent critical sections. ARace can be directly applied to binary code and requires neither additional compiler support nor hardware support. In addition, an implementation based on dynamic binary instrumentation is also proposed. The experimental results demonstrate that ARace guarantees the tolerance and detection of asymmetric races while incurring acceptable performance and memory overhead.

关键词：非对称数据竞争容忍和检测写缓冲区页保护动态二进制插桩

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On-Chip Generating FPGA Configuration Bitstreams to Reduce Applycation-Independent Test Time

On-Chip Generating FPGA Configuration Bitstreams to Reduce A...

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The 4th International Workshop on Advanced Technologies in Programmable system on Chip(第四届片上可编程系统前沿技术研讨会)

作者： Da Wang Fei Wang Paolo Ienne Yu Hu Dongrui Fan Haigang Yang Key Laboratory of Computer System and Architecture Institute of Computing TechnologyCASBeijing100190China System on Programmable Chip Research DepartmentInstitute of ElectronicsCASBeijing100190China Processor Architecture LaboratoryEPFLLausanneSwitzerland

FPGA application independent test is very time-consuming due to repetitively loading of test configuration bitstreams into the FPGA and applying test *** shows that over 95%of FPGA application independent test time is spent on loading the test configuration ***,reducing the number of loading times could significantly reduce the FPGA test *** this paper,a new approach which can significantly reduce the FPGA test time will be *** this new approach,a configuration SRAM routing strategy is used first to enhance the correlation of the test bitstream configurations,then,on-chip test configuration generation structures are designed to transform a test bitstream configuration into other ones within limited *** results show that the proposed technique can at least reduce the configuration loading time by 81%,while getting 100%test *** hardware overhead is less than 1.2%upon the whole chip without any performance penalty.

关键词： FPGA test test configuration generation design-for-testability

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A novel abstraction-guided simulation approach using posterior probabilities for verification

A novel abstraction-guided simulation approach using posteri...

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International Symposium on VLSI Design, Automation and Test

作者： Jian Wang Huawei Li Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

This paper presents a novel abstraction-guided simulation approach for multiple target states which uses posterior probabilities of the states from the abstract model, instead of abstract distances used by former abstraction-guided approaches, as the guidance of simulation. The posterior probabilities carry more precise information of the abstract model, being able to offer more effective guidance as well as allow the simulation to deal with multiple target states at a time. Experimental results show that the simulation using posterior probabilities as guidance is much more efficient than that using the abstract distances, and the multiple target states simulation framework reduces the simulation cycles effectively.

关键词： Abstracts Latches Vectors Data models Concrete Engines Markov processes

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BigDataBench: A big data benchmark suite from internet services

BigDataBench: A big data benchmark suite from internet servi...

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20th IEEE International Symposium on High Performance computer architecture, HPCA 2014

作者： Wang, Lei Zhan, Jianfeng Luo, Chunjie Zhu, Yuqing Yang, Qiang He, Yongqiang Gao, Wanling Jia, Zhen Shi, Yingjie Zhang, Shujie Zheng, Chen Lu, Gang Zhan, Kent Li, Xiaona Qiu, Bizhu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Dropbox United States Huawei China Tencent China Baidu China Yahoo United States University of Chinese Academy of Sciences China

ISBN: (纸本)9781479930975

As architecture, systems, and data management communities pay greater attention to innovative big data systems and architecture, the pressure of benchmarking and evaluating these systems rises. However, the complexity, diversity, frequently changed workloads, and rapid evolution of big data systems raise great challenges in big data benchmarking. Considering the broad use of big data systems, for the sake of fairness, big data benchmarks must include diversity of data and workloads, which is the prerequisite for evaluating big data systems and architecture. Most of the state-of-the-art big data benchmarking efforts target evaluating specific types of applications or system software stacks, and hence they are not qualified for serving the purposes mentioned above. © 2014 IEEE.

关键词： Big data

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Predoop: Preempting reduce task for job execution accelerations

Lecture Notes in Computer Science (including subseries Lectu...

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2014年 8807卷 167-180页

作者： Liang, Yi Wang, Yufeng Fan, Minglu Zhang, Chen Zhu, Yuqing Department of Computer Science Beijing University of Technology Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy Sciences Beijing China

ISBN: (纸本)9783319130200

Map/Reduce is a popular parallel processing framework for data intensive computing. For overlapping the Map task’s execution phase and the Reduce task’s intermediate data fetching and merging phase, existing Map/Reduce schedulers always pre-launch the Reduce task at the specific threshold where its map tasks have been launched, and this pattern incurs the occupation of the consuming resources of the reduce task during its idle time on waiting for fetching the intermediate data from map tasks. To address this issue, we propose an extension version of Hadoop map/reduce framework, called Predoop, in this paper. The basic idea of Predoop is to preempt the reduce task during its idle time and allocate the released resource to the map tasks on schedule. To achieve this goal, first, we introduce the preemptive mechanism for reduce tasks and map tasks respectively to enable Map/Reduce tasks to be preempted or resumed with correct status;second, we adopt the preempting-resuming model for the reduce task with the consideration of the progress of Reduce task data fetching & merging and the Map task execution so as to determine the timing of Reduce task preemption and resuming;third, we introduce the preemption-aware task scheduling strategy to allocate the released resources to the on-schedule Map tasks with the consideration of data locality. Experimental result demonstrates that Predoop outperforms Hadoop on various workload and the average job turnaround time can be reduced by maximum of 66.57%. © Springer International Publishing Switzerland 2014.

关键词： Multitasking

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SeaBase: An Implementation of Cloud Database

SeaBase: An Implementation of Cloud Database

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International Conference on Semantics, Knowledge and Grid (SKG)

作者： Shusheng Guo Zimu Yuan Li Zha Zhiwei Xu State Key Laboratory of Computer System and Architecture University of Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479967162

Cloud database usually refers to a database based on the cloud computing technology. However, as far as we know, pre-existing solutions of cloud database cannot integrate the data from multi-sourced heterogeneous databases, only supplying an isolated homogeneous database cluster. This paper presents a new implementation approach for cloud database: Sea Base, which integrates various data types into a unified one, based on the CCEVP(Cloud computing-based Effective-Virtual-Physical) model. The results of our experiments show that Sea Base is feasible and practical.

关键词： Databases Cloud computing Computational modeling Data integration computers computer architecture Data models

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A Method to Check Liveness of WS3PR 33

A Method to Check Liveness of WS3PR

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第三十三届中国控制会议

作者： WANG ShouGuang LIU Miao ZHOU MengChu WU WenHui IEEE School of Information & Electronic Engineering Zhejiang Gongshang University State Key Laboratory for Manufacturing Systems Engineering Xi’an Jiaotong University School of Electro-Mechanical Engineering Xidian University The Key Laboratory of Embedded System and Service Computing Ministry of EducationTongji University Department of Electrical and Computer Engineering New Jersey Institute of TechnologyNewarkNJ 07102USA

ISBN: (纸本)9781479947249

Petri nets are widely used to model flexible manufacturing systems(FMSs) because they can help analyze the properties and synthesize deadlock-free supervisory controllers of *** system of Simple Sequential Processes with Resources(WS3PR) is an important subclass of Petri nets that can well model many *** work first gives new algorithms to check liveness for a WS3 PR net via its subnet trees and *** the computation complexity for the proposed method is shown in this paper,to be polynomial under certain ***,sufficient conditions for deciding liveness of a WS3 PR are *** example is used to illustrate the results.

关键词： Liveness,flexible manufacturing system,deadlock,Petri net.

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Performance Optimization of Code Testing system Based on Dynamic File Cache

Performance Optimization of Code Testing System Based on Dyn...

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2014 International Conference on Artificial,Intelligence and Software Engineering(AISE 2014)

作者： Jiao-xian XU Ya-wen WANG Jun-fei HUANG Yun-zhan GONG State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences

To reduce the consumption of time when testing a C project using Code Testing system(CTS), this paper puts forward a performance optimization method based on dynamic file cache. Cache Estimation Model, which calculates the size of the file cache, is the core of this optimization method. It makes dissimilar C projects get different cache size, which shows the cache of CTS has the ability to dynamically change its size. Experimental results of four open source C projects show that the optimization method proposed in this paper can effectively improve the time performance of CTS.

关键词： Unit testing File cache Dynamic Performance optimization

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