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2013 IEEE International Conference on Automation Science and Engineering, CASE 2013

作者： Xia, Yunni Zhou, Mengchu Luo, Xin Zhu, Qingsheng Software Theory and Technology Chongqing Key Lab Chongqing University Chongqing 400030 China Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 201804 China Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102 United States

ISBN: (纸本)9781479915156

Cloud computing is a recently developed new technology for complex systems with massive service sharing, which is different from the resource sharing of the grid computing systems. In a cloud environment, service requests from users go through numerous provider specific steps from the instant it is submitted to when the service is fully delivered. Quality modeling and analysis of clouds are not easy tasks because of the complexity of the provisioning mechanism and the dynamic cloud environment. This study proposes an analytical modelbased approach for quality evaluation of Infrastructure-as-a-Service cloud and consider expected request completion time, rejection probability, and system overhead rate as key QoS metrics. It also features with the modeling of different warming and cooling strategies of machines and the ability to identify the optimal balance between system overhead and performance. © 2013 IEEE.

关键词： Quality control

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Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor

Fetching Primary and Redundant Instructions in Turn for a Fa...

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Pacific Rim International Symposium on Dependable computing

作者： Shijian Zhang Weiwu Hu Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

With the development of semiconductor technology, microprocessors become more and more susceptible to transient faults. Some proposed schemes support redundant execution of a program in a superscalar processor for fault tolerance. However, they require a huge queue to accommodate interim states, which enlarge the hardware cost significantly. This paper analyzes the effect of halving a processor¿s instruction fetch bandwidth on a program¿s performance. We find that the performance degradation resulted from halving instruction fetch bandwidth declines when instruction latency is lengthened, branch prediction accuracy deteriorates or cache miss rate increases. Since an embedded microprocessor is characterized by long instruction latency, high branch misprediction rate and cache miss rate, a fault-tolerant scheme is proposed, in which two threads fetch instructions in turn and execute in the same processor core simultaneously without any extra queue. The simulation results from eight embedded applications show that performance penalty of our solution ranges from 6.5% to 30.1%, with an average of 22.5%, which is lower than that of the other proposed schemes. The experiment also indicates that our scheme can effectively detect faults occurring in the entire pipeline with short fault detection latency and minimal hardware cost. It is well suited for our solution to realize a reliable embedded microprocessor.

关键词： Fault tolerance Microprocessors Delay Hardware Costs Bandwidth Fault detection Performance analysis Degradation Accuracy

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SeaBase: An Implementation of Cloud Database

SeaBase: An Implementation of Cloud Database

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International Conference on Semantics, Knowledge and Grid (SKG)

作者： Shusheng Guo Zimu Yuan Li Zha Zhiwei Xu State Key Laboratory of Computer System and Architecture University of Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479967162

Cloud database usually refers to a database based on the cloud computing technology. However, as far as we know, pre-existing solutions of cloud database cannot integrate the data from multi-sourced heterogeneous databases, only supplying an isolated homogeneous database cluster. This paper presents a new implementation approach for cloud database: Sea Base, which integrates various data types into a unified one, based on the CCEVP(Cloud computing-based Effective-Virtual-Physical) model. The results of our experiments show that Sea Base is feasible and practical.

关键词： Databases Cloud computing Computational modeling Data integration computers computer architecture Data models

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A 1.2 V,3.1%3σ-accuracy thermal sensor analog front-end circuit in 12 nm CMOS process

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Journal of Semiconductors 2021年第3期42卷 54-59页

作者： Liqiong Yang Linfeng Wang Junhua Xiao Longbing Zhang Jian Wang State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China University of Chinese Academy of Sciences Beijing 100049China Loongson Technology Corporation Limited Beijing 100095China

This paper presents a 1.2 V high accuracy thermal sensor analog front-end circuit with 7 probes placed around the microprocessor *** analog front-end consists of a BGR(bandgap reference),a DEM(dynamic element matching)control,and *** BGR generates the voltages linear changed with temperature,which are followed by the data read out *** superior accuracy of the BGR’s output voltage is a key factor for sensors fabricated via the FinFET digital ***,a 4-stage folded current bias structure is proposed,to increase DC accuracy and confer immunity against FinFET process variation due to limited device length and low current *** the same time,DEM is also adopted,so as to filter out current branch *** been fabricated via a 12 nm FinFET CMOS process,200 chips were *** measurement results demonstrate that these analog front-end circuits can work steadily below 1.2 V,and a less than 3.1%3σ-accuracy level is *** stability is 0.088 mV/℃across a range from-40 to 130℃.

关键词： CMOS FinFET process microprocessor thermal sensor BGR 4-stage folded

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A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems 12

A clustering-based scheme for concurrent trace in debugging ...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Jianliang Gao Jianxin Wang Yinhe Han Lei Zhang Xiaowei Li School of Information Science and Engineering Central South University China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9783981080186

Concurrent trace is an emerging challenge when debugging multicore systems. In concurrent trace, trace buffer becomes a bottleneck since all trace sources try to access it simultaneously. In addition, the on-chip interconnection fabric is extremely high hardware cost for the distributed trace signals. In this paper, we propose a clustering-based scheme which implements concurrent trace for debugging Network-on-Chip (NoC) based multicore systems. In the proposed scheme, a unified communication framework eliminates the requirement for interconnection fabric which is only used during debugging. With clustering scheme, multiple concurrent trace sources can access distributed trace buffer via NoC under bandwidth constraint. We evaluate the proposed scheme using Booksim and the results show the effectiveness of the proposed scheme.

关键词： Multicore processing Bandwidth Fabrics Debugging Clustering algorithms Real time systems system-on-a-chip

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Makespan and Security-Aware Workflow Scheduling for Cloud Service Cost Minimization Using Firefly Optimizer 22nd

Makespan and Security-Aware Workflow Scheduling for Cloud ...

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22nd International Conference on Algorithms and architectures for Parallel Processing, ICA3PP 2022

作者： Zhou, Chengliang Wang, Tian Li, Liying Sun, Jin Zhou, Junlong School of Computer Science and Engineering Nanjing University of Science and Technology Nanjing210094 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China National Trusted Embedded Software Engineering Technology Research Center East China Normal University Shanghai200062 China

ISBN: (纸本)9783031226762

As efficient commercial information technology, cloud computing has attracted more and more users to submit their requests to the cloud platform and pay for them based on the amount and quality of services. One of the most important concerns of cloud service providers is to minimize the monetary cost for completing users’ requests while meeting constraints on the quality of services such as makespan and security. To solve this concern, this paper proposes a makespan and security-aware workflow scheduling method based on an improved firefly optimizer that consists of a new solution initialization scheme, a firefly position updating scheme, a firefly-to-solution mapping operator, and two task-to-virtual machine assignment schemes. We carry out extensive simulation experiments on real-world workflows to validate our proposed workflow scheduling method. The results reveal that the monetary cost reduction achieved by our method can be up to 54.0% compared to a baseline and two state-of-the-art approaches. © 2023, Springer Nature Switzerland AG.

关键词： Cloud computing

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Acorns: A Framework for Accelerating Deep Neural Networks with Input Sparsity 19

Acorns: A Framework for Accelerating Deep Neural Networks wi...

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Proceedings of the International Conference on Parallel architectures and Compilation Techniques

作者： Xiao Dong Lei Liu Peng Zhao Guangli Li Jiansong Li Xueying Wang Xiaobing Feng State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China and University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781728136134

Deep neural networks have been employed in a broad range of applications, including face detection, natural language processing, and autonomous driving. Yet, the neural networks with the capability to tackle real-world problems are intrinsically expensive in computation, hindering the usage of these models. Sparsity in the input data of neural networks provides an optimizing opportunity. However, harnessing the potential performance improvement on modern CPU faces challenges raised by sparse computations of the neural network, such as cache-unfriendly memory accesses and efficient sparse kernel *** this paper, we propose Acorns, a framework to accelerate deep neural networks with input sparsity. In Acorns, sparse input data is organized into our designed sparse data layout, which allows memory-friendly access for kernels in neural networks and opens the door for many performance-critical optimizations. Upon that, Acorns generates efficient sparse kernels for operators in neural networks from kernel templates, which combine directions that express specific optimizing transformations to be performed, and straightforward code that describes the *** evaluations demonstrate Acorns can outperform state-of-the-art baselines by significant speedups. On the real-world detection task in autonomous driving, Acorns demonstrates 1.8-22.6× performance improvement over baselines. Specifically, the generated programs achieve 1.8-2.4× speedups over Intel MKL-DNN, 3.0-8.8× speedups over TensorFlow, and 11.1-13.2× speedups over Intel MKL-Sparse.

关键词： Compiler

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SEER: A Time Prediction Model for CNNs from GPU Kernel's View 21

SEER: A Time Prediction Model for CNNs from GPU Kernel's Vie...

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Proceedings of the 30th International Conference on Parallel architectures and Compilation Techniques

作者： Guodong Liu Sa Wang Yungang Bao State Key Laboratory of Computer Architecture Institute of Computing Technology Beijing China and University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Beijing China University of Chinese Academy of Sciences Beijing China and Institute of Computing Technology (Nanjing) Chinese Academy of Sciences Nanjing China State Key Laboratory of Computer Architecture Institute of Computing Technology Beijing China University of Chinese Academy of Sciences Beijing China and Peng Cheng Laboratory Shenzhen China

ISBN: (纸本)9781665442787

With the deepening of research and increasing size of data sets, deep neural networks have become larger and larger. To reduce the training time of large neural networks, researchers propose to optimize neural networks from different levels. When performing optimizations, prior knowledge about execution time of each part of the network can help avoid repeatedly time-consuming testing and profiling process. However it is quite challenging to build an accurate iteration time prediction model, due to opaque underlying implementation of network operators and complex architecture of accelerators. In this paper, we propose SEER, an iteration time prediction model for CNNs, targeting on GPU platforms. We propose to categorize convolution kernels into three different types: Compute-bound, DRAM-bound and Under-utilized, then we build performance model for each type respectively. We combined analytical models and learning-based models to make the performance model accurate and in line with GPU execution model. Experimental results show that, our model achieves 14.71% prediction error on convolution kernels and up to 1.79% prediction error for the overall computation time in one iteration of common CNNs. Besides, when used for selecting the best convolution algorithm, our model shows 7.14% lower error rate than cuDNN's official algorithm picker.

关键词： GPU

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Identification Algorithm Framework and Structural model on Input Pattern of Metamorphic Relations 9

Identification Algorithm Framework and Structural model on I...

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9th International Conference on Dependable systems and Their Applications, DSA 2022

作者： Yan, Shiyu Yang, Xiaohua Lu, Zhongjian Li, Meng Gong, Helin Liu, Jie Computer School University of South China Hunan Hengyang China Intelligent Equipment Software Evaluation Engineering Technology Research Center of Hunan Hengyang China Cnnc Key Laboratory on High Trusted Computing Hunan Hengyang China Nuclear Power Institute of China Science and Technology on Reactor System Design Technology Laboratory Chengdu China

ISBN: (数字)9781665488778

ISBN: (纸本)9781665488778

Metamorphic Relation (MR) plays a crucial role in Metamorphic Testing (MT), which can be regarded as the implication relation from the input pattern to the output pattern. Based on MR's properties, the identification of Metamorphic Relations (MRs) can be from its input pattern and output pattern, respectively. However, the finding of the effective input pattern is very first and important. Especially for complicated mathematical function includes more than two input variables, we systematically analyze the structural model of input pattern in MR, propose the concept of the class of basic input pattern, as well as prove that any one input pattern can be expressed as a combination of basic input patterns in scientific computing programs. Moreover, the structural model of input pattern in MR is established based on previous proof. Finally, we put forward an identification algorithm framework and analysis its complexity. The core contribution of our method is to decompose the input pattern identification problem in multi-dimensional space into a single one-dimensional. For this reason, the examples show that the complexity of the algorithm is reduced significantly. © 2022 IEEE.

关键词： Computational complexity

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architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File

Architecture Level Energy Modeling and Optimization for Mult...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Ge Zhang Xu Yang Yiwei Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Information and Technology University of International Relations UIR Beijing China

In modern high performance microprocessors, multi-ported register-files are commonly used and critical in both performance and energy consumption. As capability and issue width of register-file grows, its energy consumption increases rapidly. Much prior work about energy-efficient register-file design is focusing on various low levels except for architecture level. In this paper, an accurate architectural level energy model for register-file is proposed and verified, based on which some efficient and practical improvements are presented to save energy without changing the internal circuits or structure of register-file. We implemented a full-customized 64-bit width 64-entry depth physical register-file with 8 read ports and 4 write ports, whose power is as low as 20 mW, in a 1 GHz 4-issue out-of-order 64-bit MIPS microprocessor, Godson-2 [1], using 90 nm CMOS process. 56.0% of reading energy and 20.3% of writing energy can be saved.

关键词： Circuits computer architecture Energy consumption Microprocessors Registers Energy efficiency Out of order CMOS process Writing Semiconductor device modeling

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