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Supercomputing Conference

作者： Guangming Tan Linchuan Li Sean Triechle Everett Phillips Yungang Bao Ninghui Sun Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Nvidia Corporation India

In this paper we present a thorough experience on tuning double-precision matrix-matrix multiplication (DGEM-M) on the Fermi GPU architecture. We choose an optimal algorithm with blocking in both shared memory and registers to satisfy the constraints of the Fermi memory hierarchy. Our optimization strategy is further guided by a performance modeling based on micro-architecture benchmarks. Our optimizations include software pipelining, use of vector memory operations, and instruction scheduling. Our best CUDA algorithm achieves comparable performance with the latest CUBLAS library. We further improve upon this with an implementation in the native machine language, leading to 20% increase in performance. That is, the achieved peak performance (efficiency) is improved from 302Gflop/s (58%) to 362Gflop/s (70%).

关键词： Graphics processing unit Registers Bandwidth Instruction sets Optimization Memory management

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Distributed Fault-tolerant Tracking Control for Multi-agent system in the Environments with Obstacles 35

Distributed Fault-tolerant Tracking Control for Multi-agent ...

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第35届中国控制会议

作者： HUANG Jie ZHOU Ning CHEN Hongzhi Faculty of Mathematics and Natural Sciences University of Groningen Institute of the Cloud Computing and Big Data for Smart Agriculture and Forestry College of Computer and Information SciencesFujian Agriculture and Forestry University State Key Laboratory of Hybrid Process Industry Automation System and Equipment Technology China Iron and Steel Research Institute Group

ISBN: (纸本)9781509009107

This paper investigates the problem of collision-free coordination tracking control for multi-agent system under modeling uncertainties,actuator faults and *** syncretizing the Null-Space-based Behavioral(NSB) control and finite-time control method,a novel reference velocity signal is predesigned to achieve finite-time obstacle avoidance and coordination *** a set of finite-time coordination control laws are presented to guarantee all the agents to track a dynamic target while avoiding obstacles/***,numerical simulation is presented to demonstrate the efficacy of the control strategy.

关键词： Distributed Control Obstacle Avoidance Fault-tolerant Control Finite-time Control Modeling Uncertainties

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Instruction level test for parallel multipliers

Instruction level test for parallel multipliers

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15th IEEE International Conference on Electronics, Circuits and systems, ICECS 2008

作者： Lin, Ma. Yan, Gao Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704-25 Beijing 100190 China College of Electronics and Information Engineering Tongji University SiPing Road 1239 Shanghai 200092 China Graduate University of Chinese Academy of Science Beijing 100049 China

ISBN: (纸本)9781424421824

Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test results. But for the multipliers, one important part of microprocessors, there is no detail on how to testing them. This paper presents an instruction level test approach for the multiplier test. The proposed approach does not modify the multipliers and does not need any extra logic just using instructions of the processors to test processors' multipliers. Sequentially it does not have any test cost on area or timing. Moreover the instruction-level test is suited for at-speed test in nature. Experimental results on the real processor's circuits show that the instruction level test approach has good effect on parallel multipliers © 2008 IEEE.

关键词： system-on-chip

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Localized random access scan: Towards low area and routing overhead

Localized random access scan: Towards low area and routing o...

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Asia and South Pacific Design Automation Conference

作者： Yu Hu Xiang Fu Xiaoxin Fan Hideo Fujiwara Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Graduate School of Information Science Nara Institute of Science and Technology Ikoma Nara Japan

ISBN: (纸本)9781424419210

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.

关键词： Routing Flip-flops Circuit testing Power dissipation Read-write memory Wires Random access memory Circuit synthesis Signal synthesis Design for testability

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BuildEnVR: An Immersive Analysis system for Environmental Field 30

BuildEnVR: An Immersive Analysis System for Environmental Fi...

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30th IEEE International Conference on Parallel and Distributed systems, ICPADS 2024

作者： Zhou, Zhenghan Liu, Kebin Xie, Yantong Jin, Hangxu Liu, Shi Wang, Ruiqing Zhao, Haitian Lin, Borong Mu, Xiaofang Qi, Hui Tsinghua University Global Innovation Exchange China Fuzhou Fuyao Institute for Advanced Study China Carnegie Mellon University School of Architecture United States Tsinghua University School of Architecture China Taiyuan Normal University College of Computer Science and Technology China Shanxi Key Laboratory of Intelligent Optimization Computing and Blockchain Technology China

ISBN: (纸本)9798331515966

Amidst global warming and escalating extreme weather events, indoor environmental quality's impact on human health and public hygiene gains prominence. Environmental parameters exist essentially as fields, which are characterized by high dimensionality, density and complexity, and contain massive amounts of information in space. To facilitate visualization and analysis of indoor environmental field, we design and implement BuildEnVR, an immersive analysis system by virtual reality, enabling remote analysis of real-time and historical environmental field data. Grounded in user needs and cognitive psychology, three visualization modes emerge: the Virtual Sensor mode enables users to access perceptual data in real-time at any 3D coordinates in ambient space, the 4D Heatmap mode visualizes spatial variations and trends over time in environmental field data, and the Synaesthesia mode realizes the fusion display of multi-dimensional environmental field data, allowing users to quickly understand the overall condition of the indoor environment with a low cognitive load. Extensive user surveys validate BuildEnVR's intuitiveness and precision, and it is suitable for both experts and general users. © 2024 IEEE.

关键词： Indoor air pollution

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GPU-accelerated fault simulation and its new applications

GPU-accelerated fault simulation and its new applications

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International Symposium on VLSI Design, Automation and Test

作者： Huawei Li Dawen Xu Kwang-Ting Cheng Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

GPUs have recently been explored as a new general-purpose computing platform, which are suitable for the acceleration of compute-intensive EDA applications. In this paper we describe a GPU-based one- to n-detection fault simulator for both stuck-at and transition faults, which demonstrates a 20X speedup over a commercial CPU-based fault simulator. We further show new fault-simulation-based test selection applications enabled by this accelerated fault simulation. Our results demonstrate that the tests selected from the applications achieve higher fault coverages for 1-to-n detections with steeper fault coverage curves, as well as a better delay test quality, in comparison with tests deterministically generated by commercial ATPG tools.

关键词： Circuit faults Graphics processing unit Instruction sets Delay Integrated circuit modeling Logic gates Computational modeling

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Detecting and Eliminating Potential Violations of Sequential Consistency for Concurrent C/C++ Programs 09

Detecting and Eliminating Potential Violations of Sequential...

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International Symposium on Code Generation and Optimization (CGO)

作者： Yuelu Duan Xiaobing Feng Lei Wang Chao Zhang Pen-Chung Yew Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Computer Science and Engineering University of Minnesota Twin-Cities Minneapolis USA

ISBN: (纸本)9780769535760

When a concurrent shared-memory program written with a sequential consistency (SC) model is run on a machine implemented with a relaxed consistency (RC) model, it could cause SC violations that are very hard to debug. To avoid such violations, programmers need to provide explicit synchronizations or insert fence instructions. In this paper, we propose a scheme to detect and eliminate potential SC violations by combining Shasha/Snir's conflict graph and delay set theory with existing data race detection techniques. For each execution, we generate a race graph, which contains the improperly synchronized conflict accesses, called race accesses, and race cycles formed with those accesses. As a race cycle would probably lead to a non-sequential-consistent execution, we call it a potential violation of sequential consistency (PVSC) bug. We then compute the race delays of race cycles, and suggest programmers to insert fences into source code to eliminate PVSC bugs. We further convert a race graph into a PC race graph, and improves cycle detection and race delay computation to O(n 2 ), where n is the number of race access instructions. We evaluate our approach with the SPLASH-2 benchmarks, two large real-world applications (MySQL and Apache), and several multi-threaded Cilk programs. The results show that (1) the proposed approach could effec-tively detect PVSC bugs in real-world applications with good scalability; (2) it retains most of the performance of the concurrent program after inserting required fence instructions, with less than 6.3% performance loss; and (3) the additional cost of our approach over traditional race detection techniques is quite low, with 3.3% on average.

关键词： Programming profession Delay Set theory computer bugs Performance loss Chaos computer science Laboratories Concurrent computing computer architecture

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A Method to Check Liveness of WS3PR 33

A Method to Check Liveness of WS3PR

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第三十三届中国控制会议

作者： WANG ShouGuang LIU Miao ZHOU MengChu WU WenHui IEEE School of Information & Electronic Engineering Zhejiang Gongshang University State Key Laboratory for Manufacturing Systems Engineering Xi’an Jiaotong University School of Electro-Mechanical Engineering Xidian University The Key Laboratory of Embedded System and Service Computing Ministry of EducationTongji University Department of Electrical and Computer Engineering New Jersey Institute of TechnologyNewarkNJ 07102USA

ISBN: (纸本)9781479947249

Petri nets are widely used to model flexible manufacturing systems(FMSs) because they can help analyze the properties and synthesize deadlock-free supervisory controllers of *** system of Simple Sequential Processes with Resources(WS3PR) is an important subclass of Petri nets that can well model many *** work first gives new algorithms to check liveness for a WS3 PR net via its subnet trees and *** the computation complexity for the proposed method is shown in this paper,to be polynomial under certain ***,sufficient conditions for deciding liveness of a WS3 PR are *** example is used to illustrate the results.

关键词： Liveness,flexible manufacturing system,deadlock,Petri net.

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A stochastic method for controlling the scaling parameters of Cauchy mutation in fast evolutionary programming

A stochastic method for controlling the scaling parameters o...

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Congress on Evolutionary Computation

作者： Yunji Chen Ke Tang Tianshi Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Nature Inspired Computation and Applications Laboratory Department of Computer Science and Technology University of Science and Technology of China Hefei Anhui China

The fast evolutionary programming (FEP) introduced the Cauchy distribution into its mutation operator, thus the performances of EP were promoted significantly on a number of benchmark problems. However, the scaling parameter of the Cauchy mutation is invariable, which has become an obstacle for FEP to reach better performance. This paper proposes and analyzes a new stochastic method for controlling the variable scaling parameters of Cauchy mutation. This stochastic method collects information from a group of individuals randomly selected from the population. Empirical evidence validates our method to be very helpful in promoting the performance of FEP.

关键词： Stochastic processes Genetic mutations Genetic programming Laboratories Random variables Gaussian distribution Control systems Stochastic systems computer architecture computer applications

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Domain knowledge discovery from abstracts of scientific literature on Nickel-based single crystal superalloys

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Science China(Technological Sciences) 2023年第6期66卷 1815-1830页

作者： LIU Yue DING Lin YANG ZhengWei GE XianYuan LIU DaHui LIU Wei YU Tao AVDEEV Maxim SHI SiQi School of Computer Engineering and Science Shanghai UniversityShanghai 200444China Shanghai Engineering Research Center of Intelligent Computing System Shanghai 200444China State Key Laboratory of Advanced Special Steel&Shanghai Key Laboratory of Advanced Ferrometallurgy&School of Materials Science and Engineering Shanghai UniversityShanghai 200444China Materials Genome Institute Shanghai UniversityShanghai 200444China Institute of Functional Materials Central Iron&Steel Research InstituteBeijing 100081China Australian Nuclear Science and Technology Organisation Locked Bag 2001Kirrawee DC NSW 2232Australia School of Chemistry The University of SydneySydney 2006Australia Zhejiang Laboratory Hangzhou 311100China

Despite the huge accumulation of scientific literature,it is inefficient and laborious to manually search it for useful information to investigate structure-activity ***,we propose an efficient text-mining framework for the discovery of credible and valuable domain knowledge from abstracts of scientific literature focusing on Nickel-based single crystal ***,the credibility of abstracts is quantified in terms of source timeliness,publication authority and author’s academic ***,eight entity types and domain dictionaries describing Nickel-based single crystal superalloys are predefined to realize the named entity recognition from the abstracts,achieving an accuracy of 85.10%.Thirdly,by formulating 12 naming rules for the alloy brands derived from the recognized entities,we extract the target entities and refine them as domain knowledge through the credibility *** this,we also map out the academic cooperative“Author-Literature-institute”network,characterize the generations of Nickel-based single crystal superalloys,as well as obtain the fractions of the most important chemical elements in *** extracted rich and diverse knowledge of Nickel-based single crystal superalloys provides important insights toward understanding the structure-activity relationships for Nickel-based single crystal superalloys and is expected to accelerate the design and discovery of novel superalloys.

关键词： Nickel-based single crystal superalloys text mining named entity recognition credibility analysis domain knowledge

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