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International Conference on Networking, architecture, and Storage (NAS)

作者： Qi Ao Guojie Jin Wen Su Songsong Cai Shuai Chen State Key Laboratory of Computer Architecture Chinese Academy of Sciences Beijing Institute of Computing Technology Chinese Academy of Sciences Beijing University of Chinese Academy of Sciences Beijing Loongson Technology Corporation Limited Beijing Petrochina Oil and Gas Pipeline Control Center Beijing

A 64-bit RISC processor is designed for large applications that need large memory address. Due to the restriction of the instruction fixed length, loading a 64-bit address needs a number of instructions, leading to a penalty both of memory performance and memory consumption. This paper describes an address computation method based on hardware and software co-design. In our extended MIPS processor which supports register + register addressing, we achieve an approximate effect of memory access as their 32-bit counterparts, we propose a software load-address method, which simplifies the calculation of 64-bit address. We implement our methods in the 64-bit OpenJDK 6 on MIPS, and give both performance and consumption comparisons for SPECjvm2008 and Dacapo. The experimental results show that the performance of SPECjvm2008 is improved by 5.1%, the performance of Dacapo is improved by 7.3% and near to 24% for some benchmarks. The size of method generated by JVM compiler is reduced by an average of 13%.

关键词： Registers Software Optimization Benchmark testing Java Loading Memory management

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An efficient parallel mechanism for highly-debuggable multicore simulator

An efficient parallel mechanism for highly-debuggable multic...

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10th International Symposium on Advanced Parallel Processing Technologies, APPT 2013

作者： Ye, Xiaochun Fan, Dongrui Wang, Da Song, Fenglong Zhang, Hao Tang, Zhimin State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783642452925

Fast multicore simulators are extremely useful in evaluating design alternatives and enabling early software development. Among the state-of-the-art multicore simulators, Simics is a very popular used one both in academia and industry. It has a powerful debugging system, and also provides an accelerator to support multithreaded or distributed simulation. However, this kind of parallel mechanism mainly aims at speed up distributed systems. It is not suitable for the shared-memory multicore systems which are much more commonly used. In this paper, we propose a novel parallel mechanism to improve the simulation speed of shared-memory multicore systems. More importantly, our approach is compatible with other optimizations and exist debugging systems used in Simics. Experimental results show that our parallel approach achieves an average speedup of 9.6x (up to 12.2x) when running SPLASH-2 kernel on a 16-core host machine. © 2013 Springer-Verlag.

关键词： Simulators

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TSV Minimization for Circuit Partitioned 3D SoC Test Wrapper Design

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Journal of computer Science & technology 2013年第1期28卷 119-128页

作者： Yuan-Qing Cheng Lei Zhang Yin-He Han Xiao-Wei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100049 China

Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D system-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and

关键词： three-dimensional system-on-chip test wrapper chain through-silicon vias optimization

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Deceptive answer prediction with user preference graph

Deceptive answer prediction with user preference graph

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51st Annual Meeting of the Association for Computational Linguistics, ACL 2013

作者： Li, Fangtao Gao, Yang Zhou, Shuchang Si, Xiance Dai, Decheng Google Research Mountain View Institute of Computing Technology CAS China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS China Department of Computer Science and Technology Tsinghua University China

ISBN: (纸本)9781937284503

In Community question answering (QA) sites, malicious users may provide deceptive answers to promote their products or services. It is important to identify and filter out these deceptive answers. In this paper, we first solve this problem with the traditional supervised learning methods. Two kinds of features, including textual and contextual features, are investigated for this task. We further propose to exploit the user relationships to identify the deceptive answers, based on the hypothesis that similar users will have similar behaviors to post deceptive or authentic answers. To measure the user similarity, we propose a new user preference graph based on the answer preference expressed by users, such as "helpful" voting and "best answer" selection. The user preference graph is incorporated into traditional supervised learning framework with the graph regularization technique. The experiment results demonstrate that the user preference graph can indeed help improve the performance of deceptive answer prediction. © 2013 Association for Computational Linguistics.

关键词： Supervised learning

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Implementation and performance analysis of SDN controller

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Dongbei Daxue Xuebao/Journal of Northeastern University 2014年 35卷 313-318页

作者： Jiang, Guo-Long Wu, Jie Liu, Ke Fu, Bin-Zhang Chen, Ming-Yu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China University of Chinese Academy of Sciences Beijing100190 China

Based on the Beacon controller, this article first analyzed the implementation of the core functions of Beacon, including the switches connection, topology discovery and routing path calculation. Second, we evaluated the core functions in the controller using the Mininet Simulator and Open Switch testbed. At last, based on the routing path calculation result, we proposed a new method, named routing pool, to improve the performance. When the controller calculates the shortest path of all pairs, it calculates another path for the pair. Then the controller can push routing path directly when link failure occurs in the network, which can decrease the cost of path calculation. The results show some new light on the design and optimization for SDN controllers. ©, 2014, Northeastern University. All right reserved.

关键词： Controllers

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A Robust and Power-Effcient SoC Implementation in 65nm

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Journal of computer Science & technology 2013年第4期28卷 682-688页

作者：肖斌张译夫高燕萍杨梁吴冬梅范宝峡 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Loongson Technology Corporation Limited

Godson2H is a complex SoC （system-on-Chip） of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.

关键词： system-on-Chip on-chip-variation PVT detector low power hierarchical design flow

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H-DB: Yet another big data hybrid system of Hadoop and DBMS

H-DB: Yet another big data hybrid system of Hadoop and DBMS

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13th International Conference on Algorithms and architectures for Parallel Processing, ICA3PP 2013

作者： Luo, Tao Chen, Guoliang Zhang, Yunquan School of Computer Science and Technology University of Science and Technology of China 230027 Hefei China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS 100190 Beijing China

ISBN: (纸本)9783319038582

With the explosion of the amount of data, analytics applications require much higher performance and scalability. However, traditional DBMS encounters the tough obstacle of scalability, and could not handle big data easily. In the meantime, due to the complex relational data model, the large amount of historical data and the independent demand of subsystems, it is not suitable to use either shared-nothing MPP architecture (e.g. Hadoop) or existing hybrid architecture (e.g. HadoopDB) to replace completely. In this paper, considering the feasibility and versatility of building a hybrid system, we propose a novel prototype H-DB which takes DBMSs as the underlying storage and execution units, and Hadoop as an index layer and a cache. H-DB not only retains the analytical DBMS, but also could handle the demands of rapidly exploding data applications. The experiments show that H-DB meets the demand, outperforms original system and would be appropriate for analogous big data applications. © Springer International Publishing Switzerland 2013.

关键词： Database systems

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RSAK: Random stream attack for phase change memory in video applications

RSAK: Random stream attack for phase change memory in video ...

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2013 IEEE 31st VLSI Test Symposium, VTS 2013

作者： Fang, Yuntan Li, Huawei Li, Xiaowei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781467355438

As an emerging non-volatile memory technology, phase change memory (PCM) is promising as an alternative for traditional memories such as DRAM. In spite of its non-volatility, high density, low standby power, and resilience to soft errors, PCM has a limited write endurance or lifetime, which means that each PCM cell can only be overwritten finite times. More importantly, limited lifetime potentially provides malicious attackers an opportunity to intentionally aggravate write traffic into PCM. In this paper, from the standpoint of attackers, we propose random stream attacks (RSAK) methods for phase change memory used in video applications. Experimental results show that compared to natural video sequences, RSAK incurs higher total write traffic or worsened lifetime. RSAK also gives hints on how to build a more secure PCM in video applications to counter malicious write streams. © 2013 IEEE.

关键词： Phase change memory

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Road type estimation and hierarchical real-time vanishing point detection

Road type estimation and hierarchical real-time vanishing po...

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2013 7th International Conference on Image and Graphics, ICIG 2013

作者： Sun, Yuan Lu, Hongbo Zhang, Zhimin .State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China .University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769550503

Image-based road vanishing point (VP) detection is a challenging problem as the algorithm needs to deal with different road type with varying imaging conditions in real time. We propose a hierarchical VP detection method with the ability to choose efficient algorithms for different road types. Firstly, road scenes are classified into 4 types based on holistic road features abstracted from responses of Gabor filters, which also coarsely locate the road. Then, the distinct edge or line-like texture of each road type is adaptively extracted by a new road-line-segment detection method. Finally, VP is estimated by road-type-specific voting and verification. Experiments on 1000 general road images show that, the proposed method can detect VP under complex road scenes, achieving improvements for both accuracy and efficiency, compared with the state of the art methods relying on single features. © 2013 IEEE.

关键词： Gabor filters

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Designing a power-aware replication strategy for storage clusters

Designing a power-aware replication strategy for storage clu...

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2013 IEEE International Conference on Green computing and Communications and IEEE Internet of Things and IEEE Cyber, Physical and Social computing, GreenCom-iThings-CPSCom 2013

作者： Zhang, Lingwei Deng, Yuhui Department of Computer Science Jinan University Guangzhou 510632 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9780769550466

The exponential data growth is presenting challenges to traditional storage systems. Component-based cluster storage systems, due to their high scalability, are becoming the architecture of next generation storage systems. Cluster storage systems often use data replication to ensure high availability, fault tolerance, and load balance. However, this kind of data replication not only consumes a large amount of storage resources, but also generates more energy consumption. This paper presents a power-aware data replication strategy by leveraging data access behavior. This strategy uses 80/20 rule (80% of the data accesses often go to 20% of the storage space) to replicate only a small amount of frequently accessed data. Furthermore, the storage nodes are divided into a hot node set and a cold node set. Hot nodes, which store a small amount of hot data copies, are always in an active state to guarantee the QoS of the system. The cold nodes which store a large number of infrequently accessed cold data, are placed in a low power state, thus reducing the energy consumption of the cluster storage system. The experimental results show that the proposed strategy can effectively reduce the resource and energy consumption of the system, while ensuring the system performance. © 2013 IEEE.

关键词： Energy utilization

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