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International Conference on Multimedia, Communication and computing Application（MCCA 2014）

作者： Y.W.Yang Y.W.Wang Y.Z.Gong State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences

Library functions and system calls have been major difficulties faced by automatic ***/output(I/O) functions are a set of common library *** have to interact with the test procedures if the test program contains I/O functions,resulting in inefficient automatic *** normal functions,the association between I/O functions and operating on a specific I/O device makes ordinary stub method *** at solving this problem,this paper proposes one solution by I/O device modeling and I/O function *** semantics of the I/O functions are stored in the I/O function model,and the operations of I/O functions are similar to the I/O device *** final state and properties of the I/O device are represented by two *** the stub code is automatically generated by path-oriented stub generation *** show that this method is effective.

关键词： Automatic test Stub generation I/O modeling

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Parallel Optimization of Computational Fluid Dynamics Application code_saturne Based on Next Generation Sunway Supercomputer 14

Parallel Optimization of Computational Fluid Dynamics Applic...

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14th International Symposium on Parallel architectures, Algorithms and Programming, PAAP 2023

作者： Liu, Anjun Liao, Yin Xu, Xihao Chen, YanYan Zhong, Hongjun Wu, Jianming Kong, Bo Raikov, Alexander Guo, Meng Jinan Institute of Supercomputing Technology Jinan Key Laboratory of High Performance Industrial Software Jinan China Zhejiang Yuansuan Technology Co. Ltd Jinan Supercomputing-Zhejiang Yuansuan Industrial Simulation System Joint Laboratory Hangzhou China Qilu University of Technology Shandong Academy of Sciences Ministry of Education Shandong Computer Science Center National Supercomputer Center in Jinan Key Laboratory of Computing Power Network and Information Security China Fundamental Research Center for Computer Science Shandong Provincial Key Laboratory of Computer Networks Shandong Jinan China

ISBN: (纸本)9798350371024

code_saturne is an open-source general large-scale computational fluid dynamics software independently developed by Electricite de France since 1997. Due to its high computing performance, code_saturne has been widely used in the nuclear industry, heavy fuel and biomass combustion, particle tracking and other computational fluid dynamics fields. In this work, we implemented code_saturne on the new generation Sunway supercomputer (SW26010pro) at the first time. By applying the data value-taking technology of double cache, combined with Sunway shared memory technology, we have adapted the data structure and Modular programming of code_saturne conducively to the new generation Sunway supercomputer (SW26010pro) and accelerated the software hotspots the software hotspots by 1-2 times. After optimizing and porting, this software has successfully served in the numerical simulation of the lateral flow of fuel assemblies in the nuclear industry. © 2023 IEEE.

关键词： Supercomputers

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A Case Study on At-Speed Testing for a Gigahertz Microprocessor

A Case Study on At-Speed Testing for a Gigahertz Microproces...

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Da Wang Rui Li Yu Hu Huawei Li Xiaowei Li Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics Company Limited Shanghai China

This paper describes a low cost, high quality at-speed testing strategy implemented on a gigahertz microprocessor with multi-clock domains. The presented DFT method not only utilizes the internal phase-locked loops (PLLs) to provide complex test clock sequences, but also applies a hybrid scan compression structure to reduce test data volume. It is difficult and time-consuming to generate at-speed tests for a design with embedded memories and multi-clock domains. The proposed test pattern generation scheme can gain transition fault coverage of approximately 83% for this high-performance microprocessor, and the test power consumption is well controlled.

关键词： Microprocessors Circuit testing Clocks Logic testing system testing Electronic equipment testing Test pattern generators Costs Circuit faults Energy consumption

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Thermal-sustainable power budgeting for dynamic threading 14

Thermal-sustainable power budgeting for dynamic threading

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51st Annual Design Automation Conference, DAC 2014

作者： Hu, Xing Xu, Yi Ma, Jun Chen, Guoqing Hu, Yu Xie, Yuan State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Macau University of Science and Technology China Advanced Micro Devices Beijing China Pennsylvania State University University Park United States

ISBN: (纸本)9781479930173

As technology scales, thermal management for multi-core architectures becomes a critical challenge due to increased power density and higher integration density. Existing power budgeting techniques focus on maximizing performance under a given power budget by optimizing the core dynamics. However, in multi-core era, a chip-wide power budget is not sufficient to ensure thermal constraints because the thermal sustainable power capacity varies with different threading strategies and core configurations. In this paper, we propose a model which estimates the thermal sustainable power capacity considering these two run-time factors. The model converts the thermal effect of threading strategies and core configurations into power capacity, which provides a context-based power budget for the power budgeting. Based on this model, we introduce a power budgeting framework aiming to optimize the performance within thermal constraints, named as TSocket. Compared to the chip-wide power budgeting solution, TSocket shows 19% of performance improvement for the PARSEC benchmarks by reducing thermal violations and providing extra power budget for performance improvement. Copyright 2014 ACM.

关键词： Benchmarking

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A virtualized data center energy-saving mechanism based on switching operating mode of physical servers and reserving virtual machines

A virtualized data center energy-saving mechanism based on s...

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作者： Yin, Chunxia Liu, Jian Jin, Shunfu College of Information Science and Engineering Yanshan University Qinhuangdao China Key Laboratory for Computer Virtual Technology and System Integration of Hebei Province Yanshan University Qinhuangdao China Ocean College of Hebei Agricultural University Qinhuangdao China Institute of Computing Technology Chinese Academy of Sciences Beijing China

The energy consumption of virtualized data centers has grown very fast in last several years. Because a large number of hosts are running in an idle state, virtualized data centers waste a large amount of electric energy. To save more energy for virtualized data centers, an energy-saving mechanism is proposed based on switching operating mode of physical servers and reserving virtual machines (VMs). The main idea is that when the amount of idle VMs reaches twice of a specified threshold, half of these idle VMs are reserved to process the new task that is about to arrive, and the physical server which hosts the other half of the idle VMs is switched to the sleep mode. From the perspective of task arrival rate and sleep parameters, we use two-dimensional Markov processes to analyze the proposed energy-saving mechanisms. By using matrix geometry solutions, we theoretically estimate energy consumption and response performance. According to the numerical experiments, the proposed energy-saving mechanism obviously cut down electric energy consumption and ensures response performance. Finally, the specified threshold for the amount of VMs is optimized by building a cost function. © 2020 John Wiley & Sons, Ltd.

关键词： Cost functions

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Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-...

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Asian Test Symposium (ATS)

作者： Keheng Huang Yu Hu Xiaowei Li Gengxin Hua Hongjin Liu Bo Liu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Beijing Institute of Control Engineering China

As the feature size of FPGA shrinks to nanometers, SRAM-based FPGAs are more vulnerable to soft errors. During logic synthesis, reliability of the design can be improved by introducing logic masking effect. In this work, we observe that there are a lot of not-fully occupied look-up tables (LUTs) after logic synthesis. Hence, we propose a functional equivalent class based soft error mitigation scheme to exploit free LUT entries in the circuit. The proposed technique replaces not fully-occupied LUTs with corresponding functional equivalent classes, which can improve the reliability while preserve the functionality of the design. Experimental results show that, compared with the baseline ABC mapper, the proposed technique can reduce the soft error rate by 21%, and the critical-path delay increase is only 4.25%.

关键词： Table lookup Circuit faults Forward error correction Field programmable gate arrays Vectors Reliability engineering

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Dynamic Resource Allocation Based on User experience in Virtualized Servers

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Procedia Engineering 2011年 15卷 3780-3784页

作者： Wei Zhang Jiajun Liu Ying Song Mingfa Zhu Limin Xiao Yuzhong Sun Li Ruan State Key Laboratory of Software Development Environment Beijing 100191 China School of Computer Science and Engineering Beihang University Beijing 100191 China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing Institute of Computing Technology Chinese Academy of Sciences Beijing China

Web workloads are known to vary dynamically with time which poses a challenge to resource allocation among the applications. In this paper, we argue that the existing dynamic resource allocation based on resource utilization has some drawbacks in virtualized servers. Dynamic resource allocation directly based on real-time user experience is more reasonable and also has practical significance. To address the problem, we propose a system architecture that combines real time measurements and analysis of user experience for resource allocation. We evaluate our proposal using Webbench. The experiment results show that these techniques can judiciously allocate system resources.

关键词： resource allocation virtualized servers user experience

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BENCHIP： Benchmarking Intelligence Processors

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Journal of computer Science & technology 2018年第1期33卷 1-23页

作者： Jin-Hua Tao Zi-Dong Du Qi Guo Hui-Ying Lan Lei Zhang Sheng-Yuan Zhou Ling-Jie Xu Cong Liu Hai-Feng Liu Shah Tang Allen Rush Willian Chen Shao-Li Liu Yun-Ji Chen Tian-Shi Chen State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 100049 China Intelligent Processor Research Center Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Cambricon Ltd. Beijing 100190 China A libaba Infrastructure Service A libaba Group Hangzhou 311121 China Iflytek Co. Ltd. Hefei 230088 China Beijing Jingdong Century Trading Co. Ltd. Beijing 100176 China RDA Microdectronics Inc. Shanghai 201203 China Advanced Micro Devices Inc. Sunnyvale CA 94085 U.S.A.

The increasing attention on deep learning has tremendously spurred the design of intelligence processing hardware. The variety of emerging intelligence processors requires standard benchmarks for fair comparison and system optimization （in both software and hardware）. However, existing benchmarks are unsuitable for benchmarking intelligence processors due to their non-diversity and nonrepresentativeness. Also, the lack of a standard benchmarking methodology further exacerbates this problem. In this paper, we propose BENCHIP, a benchmark suite and benchmarking methodology for intelligence processors. The benchmark suite in BENCHIP consists of two sets of benchmarks： microbenchmarks and macrobenchmarks. The microbenchmarks consist of single-layer networks, They are mainly designed for bottleneck analysis and system optimization. The macrobenchmarks contain state-of-the-art industrial networks, so as to offer a realistic comparison of different platforms. We also propose a standard benchmarking methodology built upon an industrial software stack and evaluation metrics that comprehensively reflect various characteristics of the evaluated intelligence processors, BENCHIP is utilized for evaluating various hardware platforms, including CPUs, GPUs, and accelerators. BENCHIP will be open-sourced soon.

关键词： deep learning intelligence processor benchmark

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A relational taxonomy of services for large scale service repositories

A relational taxonomy of services for large scale service re...

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2012 IEEE 19th International Conference on Web Services, ICWS 2012

作者： Wu, Yan Yan, Chungang Ding, Zhijun Wang, Pengwei Jiang, Changjun Zhou, Mengchu Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai China Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102 United States School of Electronics and Information Engineering Tongji University Shanghai China

ISBN: (纸本)9780769547527

With the rapid development of service-oriented computing (SOC) and service-oriented architecture (SOA), the number of services is rapidly increasing. How to organize and manage services effectively in repositories to improve the efficiency of service discovery and composition is important. This paper proposes three categorization rules to classify services for a large scale repository to form a relational taxonomy. The service retrieve scope can be drastically narrowed by this taxonomy. Therefore, the efficiency of service discovery and service composition can be greatly improved. We evaluate and compare the performance of the proposed method and other related ones via a publicly available test set, ICEBE05. The experimental results validate the effectiveness and high efficiency of the proposed one. © 2012 IEEE.

关键词： Web services

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F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM 21

F3D: Accelerating 3D Convolutional Neural Networks in Freque...

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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Bosheng Liu Zhuoshen Jiang Wu Jigang Xiaoming Chen Yinhe Han Peng Liu School of Computer Science and Technology Guangdong University of Technology China and State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences Beijing China School of Computer Science and Technology Guangdong University of Technology China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781665432740

3D convolutional neural networks (CNNs) are widely deployed in video analysis. Fast algorithms such as fast Fourier transforms (FFTs) are gaining popularity in reducing computation complexity for their superior capability of replacing convolutions with simpler element-wise multiplications. Conventional frequency-domain dedicated accelerators employ memory hierarchy organization for high throughput but at the expensive costs of a significant amount of data movements and energy consumptions. This paper presents F3D, a processing-in-memory frequency-domain accelerator using resistive random access memory (ReRAM). F3D supports frequency-domain complex number multiplications directly in ReRAM-based crossbar architecture. We alleviate the overheads of redundant data movements in ReRAM-based complex number multiplications by data reuse and the inherent symmetry of inputs in the frequency space. Evaluation results demonstrate that F3D outperforms state-of-the-art accelerators with significant improvements in performance and energy efficiency.

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