Occupants' comfort is the primary target in a building operation. However their efforts are often neglected and ruled out from traditional control strategies of energy-efficient building management systems. Occupa...
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Occupants' comfort is the primary target in a building operation. However their efforts are often neglected and ruled out from traditional control strategies of energy-efficient building management systems. Occupant-engaged control strategies have recently attracted many research attentions and demonstrated great potentials for energy saving. With them, occupants' behavior is incorporated into the closed-loop control methods in which their initiatives actively contribute to building services and energy utility by explicitly expressing their preferences. This work proposes an occupant-engaged demand response (DR) strategy for building automation in which occupants are actively engaged to adapt their energy consumption in response to incentive opportunities designed by facility managers. A model-based study and a Nash-Equilibrium-based solution are provided to assist facility managers with the design of social incentive policies to promote occupant participation, along with the guarantee of lucrativeness for a DR event.
A multi-cluster tool is composed of a number of single-cluster tools linked by buffering modules. The capacity of a buffering module can be one or two. Aiming at finding an optimal one-wafer cyclic schedule, this work...
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A multi-cluster tool is composed of a number of single-cluster tools linked by buffering modules. The capacity of a buffering module can be one or two. Aiming at finding an optimal one-wafer cyclic schedule, this work explores the effect of two-space buffering modules on the performance of a multi-cluster tool. The tool is modeled by a kind of Petri nets. The dynamic behavior of robot waiting and tasks, process modules, and buffers is well captured by the net model. With the model, this work shows that there is always a one-wafer cyclic schedule that reaches the lower bound of the cycle time of a process-dominant tool. Furthermore, a constant-time algorithm is revealed to find such a schedule for the first time for such multi-cluster tools. An illustrative example is given to show the application and power of this new method.
Energy efficiency is becoming an important issue in networks. Although some research works have been devoted to this topic, only a little attention has been paid to the stability of the network equipped with the energ...
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ISBN:
(纸本)9780768550436
Energy efficiency is becoming an important issue in networks. Although some research works have been devoted to this topic, only a little attention has been paid to the stability of the network equipped with the energy conservation mechanisms. In fact, we find that the stability of networks can be undermined in the worst case if it isn't considered with care by the energy conservation *** this paper, we propose an energy-efficient scheduling protocol which can guarantee the stability of the network in all cases. We start by building a new model which can be used to verify the stability of the network equipped with the energy conservation mechanisms. With this model, we transform the packet scheduling problem to a Job Shop Scheduling problem. For this problem, we propose a time-stamp based work-conserving scheduling algorithm - G-FSA. Compared with existing methods, this scheduling algorithm guarantees a tighter bound on the make span of the jobs. Then, we integrate G-FSA with a time partition approach to generate our energy-efficient packet scheduling protocol. It is proved that the obtained protocol can guarantee the stability of network in all cases. And its approximation ratio in terms of energy efficiency can be bounded by O((1+ )) for any > 0, where is an input parameter depending on the hardware infrastructure. Typically, 1
It is desired to require a walking robot for the elderly and the disabled to have large capacity,high stiffness,stability,***,the existing walking robots cannot achieve these requirements because of the weight-payload...
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It is desired to require a walking robot for the elderly and the disabled to have large capacity,high stiffness,stability,***,the existing walking robots cannot achieve these requirements because of the weight-payload ratio and simple ***,Improvement of enhancing capacity and functions of the walking robot is an important research *** to walking requirements and combining modularization and reconfigurable ideas,a quadruped/biped reconfigurable walking robot with parallel leg mechanism is *** proposed robot can be used for both a biped and a quadruped walking *** kinematics and performance analysis of a 3-UPU parallel mechanism which is the basic leg mechanism of a quadruped walking robot are conducted and the structural parameters are *** results show that performance of the walking robot is optimal when the circumradius R,r of the upper and lower platform of leg mechanism are 161.7 mm,57.7 mm,*** on the optimal results,the kinematics and dynamics of the quadruped walking robot in the static walking mode are derived with the application of parallel mechanism and influence coefficient theory,and the optimal coordination distribution of the dynamic load for the quadruped walking robot with over-determinate inputs is analyzed,which solves dynamic load coupling caused by the branches’ constraint of the robot in the walk *** laying a theoretical foundation for development of the prototype,the kinematics and dynamics studies on the quadruped walking robot also boost the theoretical research of the quadruped walking and the practical applications of parallel mechanism.
A 64-bit RISC processor is designed for large applications that need large memory address. Due to the restriction of the instruction fixed length, loading a 64-bit address needs a number of instructions, leading to a ...
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A 64-bit RISC processor is designed for large applications that need large memory address. Due to the restriction of the instruction fixed length, loading a 64-bit address needs a number of instructions, leading to a penalty both of memory performance and memory consumption. This paper describes an address computation method based on hardware and software co-design. In our extended MIPS processor which supports register + register addressing, we achieve an approximate effect of memory access as their 32-bit counterparts, we propose a software load-address method, which simplifies the calculation of 64-bit address. We implement our methods in the 64-bit OpenJDK 6 on MIPS, and give both performance and consumption comparisons for SPECjvm2008 and Dacapo. The experimental results show that the performance of SPECjvm2008 is improved by 5.1%, the performance of Dacapo is improved by 7.3% and near to 24% for some benchmarks. The size of method generated by JVM compiler is reduced by an average of 13%.
Fast multicore simulators are extremely useful in evaluating design alternatives and enabling early software development. Among the state-of-the-art multicore simulators, Simics is a very popular used one both in acad...
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Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-sca...
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Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D system-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and
As the semiconductor industry advances to nano-technology points, Network on Chip (NoC) components are becoming vulnerable to errors during the system operation. Consequently, fault-tolerant techniques for NoC are nee...
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In Community question answering (QA) sites, malicious users may provide deceptive answers to promote their products or services. It is important to identify and filter out these deceptive answers. In this paper, we fi...
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Godson2H is a complex SoC （system-on-Chip） of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high ...
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Godson2H is a complex SoC （system-on-Chip） of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.
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