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Deep Reinforcement Agent for Failure-aware Job scheduling in High-Performance computing

Deep Reinforcement Agent for Failure-aware Job scheduling in...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Kang Yang Rongyu Cao Yueyuan Zhou Jiawei Zhang En Shao Guangming Tan State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665408790

Job scheduling is crucial in high-performance computing (HPC), which is dedicated to deciding when and which jobs are allocated to the system and placing the jobs on which resources, by considering multiple scheduling goals. Along with the incremental of various resources and dazzling deep learning training (DLT) workloads, job failure becomes a quite common issue in HPC, which will affect user satisfaction and cluster utilization. To alleviate the influence of hardware and software errors as much as possible, in this paper, we aim to tackle the problem of failure-aware job scheduling in HPC clusters. Inspired by the success of previous studies of deep reinforcement learning-driven job scheduling, we propose a novel HPC scheduling agent named FARS (Failure-aware RL-based scheduler) by considering the effects of job failures. On the one hand, a neural network is applied to map the information of raw cluster and job states to job placement decisions. On the other hand, to consider the influence of job failure for user satisfaction and cluster utilization, FARS leverages make-span of the entire workload as the training objective. Additionally, effective exploration and experience replay techniques are applied to obtain effectively converged agent. To evaluate the capability of FARS, we design extensive trace-based simulation experiments with the popular DLT workloads. The experimental results show that, compared with the best baseline model, FARS obtains 5.69% improvement of average make-span under different device error rates. Together, our FARS is an ideal candidate for failure-aware job scheduler in HPC clusters.

关键词： Training Deep learning Processor scheduling Error analysis Computational modeling Conferences Neural networks

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Research on Fault Diagnosis Method Based on Structural Causal Model in Tennessee Eastman Process 7th

Research on Fault Diagnosis Method Based on Structural Causa...

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7th International Conference on computing, Control and Industrial Engineering, CCIE 2023

作者： Pu, Haoyuan Liu, Jie Chen, Zhi Yang, Xiaohua Ren, Changan Xu, Zhuoran Jian, Yifan School of Computer Science University of South China Hengyang China Science and Technology on Reactor System Design Technology Laboratory Nuclear Power Institute of China Chengdu China Intelligent Equipment Software Evaluation Engineering Technology Research Center of Hunan Hengyang China CNNC Key Laboratory on High Trusted Computing Hengyang China School of Nuclear Science and Technology University of South China Hengyang China

ISBN: (纸本)9789819927296

In the practical application of fault diagnosis in large-scale chemical systems, due to the danger of faults, the machine learning diagnosis methods used in current research often face the problem of scarcity of fault samples. This makes it difficult for the model to be trained effectively, thus affecting the fault detection rate of the model. Therefore, for the fault diagnosis of chemical system with small sample data, this paper proposes a diagnostic method that uses structural causal model to further combine the diagnostic results of the two machine learning methods, thereby improving global diagnostic performance. With the help of powerful system description ability of structural causal model, we can establish a causal graph for diagnostic process of the chemical system, and accurately construct the corresponding structural equations for the various diagnostic results of the two machine learning methods to combine them, thus improve the fault detection rate. The global results make up for the shortcomings of single machine learning method in small sample chemical system fault diagnosis. The verification on the chemical system simulation platform Tennessee Eastman process shows that, compared with the diagnosis results of the selected Gaussian Naive Bayes method and the K-nearest neighbour method, the results obtained by our method are effectively improved in fault detection rate of each fault in TEP. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Failure analysis

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Reliable and Energy Efficient Protocol for Wireless Sensor Network

Reliable and Energy Efficient Protocol for Wireless Sensor N...

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第十二届全国容错计算学术会议

作者： KAN Baoqiang CAI Li XU Yongjun College of Science Air Force Engineering UniversityXi'an 710052China Key Laboratory of Computer Sy College of Science Air Force Engineering UniversityXi'an 710052China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Low-power design is one of the most important issues in wireless sensor networks (WSNs), while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make the power consumption down, but excessive interferences from potential adjacent operating links and communication reliability between nodes should be considered. In this paper, a reliable and energy efficient protocol is presented, which adopts adaptive rate control based on an optimal TP. A mathematical model considering average interference and network connectivity was used to predict the optimal TP. Then for the optimal TP, active nodes adaptively chose the data rate with the change of bit-error-rate(BER) performance. The efficiency of the new strategy was validated by mathematical analysis and simulations. Compared with 802.11 DCF which uses maximum unified TP and BASIC protocol, it is shown that the higher average throughput can achieve while the energy consumption per useful bit can be reduced according to the results.

关键词： wireless sensor networks reliable communication energy efficient optimal transmitting power adaptive link control

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GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debugging

GVE: Godson-T Verification Engine for many-core architecture...

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IEEE International Conference on Field-Programmable technology (FPT)

作者： Zhengmeng Lei Lunkai Zhang Fenglong Song Shibin Tang Dongrui Fan Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5 LX330 FPGAs, thus permitting us to map our many-core processor and peripheral devices into it. Besides the hardware, our toolkit Godson-T Studio provides the compiler, program loader, debugger and monitor to fulfil the purpose of developing, profiling and debugging, while the accuracy loss problem is settled by our novel techniques: Check-point and ILA-Check, presented in this paper. To our experience, GVE greatly reduces the verification cycle due to its high execution speed, for example, it finishes thousands of testcases in an hour, where the software-based approach takes few days to run. And by the help of the checkpoint framework, we can easily locate the faults. Because of these features, GVE makes a great contribution to the 16-tile Godson-T tape-out Project.

关键词： Clocks Field programmable gate arrays Synchronization Registers Hardware computer architecture Emulation

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Data Motif-based Proxy Benchmarks for Big Data and AI Workloads

Data Motif-based Proxy Benchmarks for Big Data and AI Worklo...

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IEEE International Workshop/Symposium on Workload Characterization

作者： Wanling Gao Jianfeng Zhan Lei Wang Chunjie Luo Zhen Jia Daoyi Zheng Chen Zheng Xiwen He Hainan Ye Haibin Wang Rui Ren State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Princeton University Beijing Academy of Frontier Sciences and Technology Huawei

For the architecture community, reasonable simulation time is a strong requirement in addition to performance data accuracy. However, emerging big data and AI workloads are too huge at binary size level and prohibitively expensive to run on cycle-accurate simulators. The concept of data motif, which is identified as a class of units of computation performed on initial or intermediate data, is the first step towards building proxy benchmark to mimic the real-world big data and AI workloads. However, there is no practical way to construct a proxy benchmark based on the data motifs to help simulation based research. In this paper, we embark on a study to bridge the gap between data motif and a practical proxy benchmark. We propose a data motif-based proxy benchmark generating methodology by means of machine learning method, which combine data motifs with different weights to mimic the big data and AI workloads. Furthermore, we implement various data motifs using light-weight stacks and apply the methodology to five real-world workloads to construct a suite of proxy benchmarks, considering the data types, patterns, and distributions. The evaluation results show that our proxy benchmarks shorten the execution time by 100s times on real systems while maintaining the average system and micro-architecture performance data accuracy above 90%, even changing the input data sets or cluster configurations. Moreover, the generated proxy benchmarks reflect consistent performance trends across different architectures. To facilitate the community, we will release the proxy benchmarks on the project homepage http://***/BigDataBench.

关键词： Benchmark testing Big Data Artificial intelligence Measurement computer architecture Data models Computational modeling

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Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis

Observation Point Oriented Deterministic Diagnosis Pattern G...

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Asian Test Symposium (ATS)

作者： Fei Wang Yu Hu Yu Huang Jing Ye Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Mentor Graphics Corporation Marlborough MA USA

Scan is a widely used Design-for-Testability technique to improve test and diagnosis quality. Many defects may cause scan chains to fail. In this paper, an observation point oriented Deterministic Diagnostic Pattern Generation (DDPG) method was proposed for compound defects, which tolerates the system defects during scan chain diagnosis. Instead of sensitizing multiple paths proposed in our prior work, the proposed new DDPG method directly targets as many observation points as possible to observe the loading error occurred on the targeted scan cell. Experimental results on ISCASpsila89 benchmark circuits show that the proposed DDPG method improves the effectiveness and efficiency of diagnosing compound defects, compared to our prior research.

关键词： Fault diagnosis system testing Circuit faults Hardware Test pattern generators Laboratories computer architecture computer graphics Logic design Timing

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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

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IEEE International Test Conference

作者： Da Wang Xiaoxin Fan Xiang Fu Hui Liu Ke Wen Rui Li Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics (Shanghai) Company Limited Shanghai China

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. ... 详细信息

关键词： Microprocessors Clocks Design for testability Circuit testing Logic testing Circuit faults Manufacturing Power dissipation CMOS technology Phase locked loops

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Modeling and analysis of dual-arm cluster tools for wafer fabrication with revisiting

Modeling and analysis of dual-arm cluster tools for wafer fa...

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2011 7th IEEE International Conference on Automation Science and Engineering, CASE 2011

作者： Qiao, Yan Wu, NaiQi Zhou, MengChu Department of Industrial Engineering School of Mechatronics Engineering Guangdong University of Technology Guangzhou 510006 China Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 200092 China Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102-1982 United States

ISBN: (纸本)9781457717307

Some wafer fabrication processes are repeated processes, e.g. atomic layer deposition (ALD) process. For such processes, the wafers need to visit some processing modules for a number of times, which complicates the cycle time analysis. This paper studies the cycle time analysis problem for such processes. With a Petri net model, it is found that such processes contain local cycles involving only the revisiting PMs and global cycles involving both revisiting and non-revisiting PMs. The process switches between these two types of cycles such that the process never reaches a steady state. Based on this finding, the mechanism underlying such processes is revealed and analytical expressions are given for the calculation of their cycle time. Illustrative examples are presented to show the application of the proposed approach. © 2011 IEEE.

关键词： Atomic layer deposition

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A cost-effective substantial-impact-filter based method to tolerate voltage emergencies

A cost-effective substantial-impact-filter based method to t...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Songjun Pan Yu Hu Xing Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution; 2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf ) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies; 3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach.

关键词： Microprocessors Delay computer architecture Computational modeling Sensors Benchmark testing

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Secure localization algorithms in wireless sensor networks: A review 2nd

Secure localization algorithms in wireless sensor networks: ...

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2nd International Conference on computer, Communication and Computational Sciences, IC4S 2017

作者： Wang, Hua Wen, Yingyou Lu, Yao Zhao, Dazhe Ji, Chunlin School of Computer Science & Engineering Northeastern University Shenyang110819 China State Key Laboratory of Software Architecture Neusoft Corporation Shenyang110179 China Beijing Jiaotong University Beijing100044 China Key Laboratory of Medical Image Computing Ministry of Education Northeastern University Shenyang110819 China Kuang-Chi Institute of Advanced Technology Shenzhen518000 China

ISBN: (纸本)9789811303432

Localization plays a vital role in understanding the application context for wireless sensor networks (WSNs). However, it is vulnerable to various threats due to the open arrangement area, the nature of radio broadcasting, and resource constraint. Two kinds of attacks on localization process need to be investigated. On the one hand, adversaries may capture, impersonate, replicate, or fabricate nodes to mislead the target to an incorrect position. On the other hand, adversaries may tamper, interfere, replay, or modify jointly localization information to disturb the localization. This paper describes two kinds of localization attacks and gives a systematic survey of existing secure localization solutions, including the design ideas, application scopes, and limitations. Next, several novel secure localization schemes for special WSNs applications, including Underwater Wireless Sensor Networks (UWSNs), Wireless Body Area Network (WBAN) and three-dimensional (3D), are analyzed. Finally, many open problems for secure localization are presented. © Springer Nature Singapore Pte Ltd. 2019.

关键词： Wireless sensor networks

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