检索结果-内蒙古大学图书馆

Asian Test Symposium (ATS)

作者： Jing Ye Xiaolin Zhang Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

Volume diagnosis plays an important role in the yield learning process. To get a high quality diagnosis result, patterns with high distinguish ability are essential. However, the test patterns used by volume diagnosis commonly have low distinguish ability to specific faults. In our experiments, we observe that on average, under automatic generated test patterns, faults in the same fan out free region (FFR) account for only 6% of all possible fault pairs, but their share in total indistinguishable faults is 70%, faults in different FFRs but with the same observation points account for 4% of all fault pairs, but their share in total indistinguishable faults is 22%. Exploiting this fact that faults in the same FFRs are harder to be distinguished, we propose an Automatic Diagnostic Pattern Generation (ADPG) method named Substantial Fault Pairs at-A-Time (SFPAT)-ADPG. By applying a transformed circuit and a new fault list to an existing Automatic Test Pattern Generation (ATPG) tool, we generate the compressed test patterns which are also the diagnostic patterns with high distinguish ability for the original circuit. Experiments on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed SFPAT-ADPG method.

关键词： Circuit faults Automatic test pattern generation Benchmark testing Logic gates Transforms Integrated circuit modeling

来源：评论

学校读者我要写书评

暂无评论

Trusted connection system based on virtual machine architecture

Trusted connection system based on virtual machine architect...

引用

International Conference on computer Science and Information technology (CSIT)

作者： Kai Zhang Ying Song Hai-feng Fang Yu-zhong Sun Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

With the rapid development of virtualization technology, virtual machine (VM) is widely used by cloud computing - the more and more popular computing paradigm. Thus, in order to guarantee the security of cloud computing, it is necessary to securely identify the kernel of VM, the software stack running on VM and the hardware platform which VM relies on. This paper designs a system of trusted connection based on virtual machine architecture and implements a system prototype. Our system not only can securely measure and identify the kernel of VM, the software stack running on VM and the hardware platform which VM relies on, but also can realize isolations to untrusted VMs. There are three main parts in our system: trusted chain, attestation and isolation. The experiments described in this paper prove that our system ensures trusted connection of VMs and achieves isolations to untrusted VMs. The performance of our system is also analyzed and evaluated. According to the analysis results, our system is practical in terms of performance.

关键词： Variable speed drives Scalability Isolators Clouds Fires

来源：评论

学校读者我要写书评

暂无评论

HPP-Controller: An intra-node controller designed for connecting heterogeneous CPUs

HPP-Controller: An intra-node controller designed for connec...

引用

IEEE International Conference on Cluster computing

作者： Qiang Li Panyong Zhang Ninghui Sun Chinese Academy and Sciences China Chinese Academy of Sciences Beijing Beijing CN National Research Center of Intelligent Computing Systems Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences China

Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. In these systems, CPU needs interact with special processing units to process data together, thus communications between these heterogeneous processing units become a key problem, and the communication subsytem should provide low latency and high bandwidth. In this paper, we propose HPP-Controller, which is designed for connecting two different types of CPUs (AMD and Loongson) in one node. It connects heterogeneous CPUs on top of no-coherent HyperTransport (HT) fabric and supports Global Physical Address Space. We implement a FPGA-based prototype and evaluate it via experiments. Initial results show that HPP-Controller has low latency of 0.75 us and high bandwidth close to bandwith of HT links.

关键词： Joining processes Central Processing Unit Delay Bandwidth Supercomputers Petascale computing Control systems Field programmable gate arrays Access protocols Sun

来源：评论

学校读者我要写书评

暂无评论

Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power

Design of Low-Cost High-Performance Floating-Point Fused Mul...

引用

International Conference on VLSI Design

作者： Zichu Qi Qi Guo Ge Zhang Xiangku Li Weiwu Hu Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

ISBN: (纸本)9781424455416

This paper presents a floating-point fused multiply-add (FMA) unit with low-cost and low power techniques. To improve the performance, two single-precision operations can be performed concurrently with one double-precision datapath, which is very useful in multimedia and even scientific applications. Moreover, to reduce the additional area costs for supporting two single-precision operations in parallel, multiple double-precision units, i.e., the multiplier, shifter and adder, are reused as much as possible. A modified dual-path algorithm is proposed by classifying the exponent difference into three cases and implementing them with close and far paths, which can reduce latency and facilitate lowering power consumption by enabling only one of the two paths. In addition, in case of FADD instructions, the multiplier in the first stage is bypassed and kept in stable mode, which can significantly improve FADD instruction performance and lower power consumption. The overall FMA unit has a latency of 4 cycles while the FADD operation has 3 cycles. Each cycle has a time delay of about 0.66 ns in the ST 65 nm CMOS technology. Compared with the conventional double-precision FMA, about 13% delay is reduced and about 22% area is increased, which is acceptable since two single-precision results can be generated simultaneously.

关键词： Costs Energy consumption CMOS technology Hardware Throughput Very large scale integration Laboratories computer architecture Delay effects Roundoff errors

来源：评论

学校读者我要写书评

暂无评论

A service-oriented priority-based resource scheduling scheme for virtualized utility computing 08

引用

Proceedings of the 15th international conference on High performance computing

作者： Ying Song Yaqiong Li Hui Wang Yufang Zhang Binquan Feng Hongyong Zang Yuzhong Sun Key Lab. of Computer System and Architecture Inst. of Computing Techn. Chinese Academy of Sciences China and National Research Center for Intelligent Computing Systems ICT China and Graduate Univ. of Chinese Academy of Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China and National Research Center for Intelligent Computing Systems ICT China

ISBN: (纸本)9783540898931

In order to provide high resource utilization and QoS assurance inutility computing hosting concurrently various services, this paper proposes aservice computing framework-RAINBOW for VM(Virtual Machine)-basedutility computing. In RAINBOW, we present a priority-based resourcescheduling scheme including resource flowing algorithms (RFaVM) to optimizeresource allocations amongst services. The principle of RFaVM is preferentiallyensuring performance of some critical services by degrading of others to someextent when resource competition arises. Based on our prototype, we evaluateRAINBOW and RFaVM. The experimental results show that RAINBOWwithout RFaVM provides 28%-324% improvements in service performance,and 26% higher the average CPU utilization than traditional service computingframework (TSF) in typical enterprise environment. RAINBOW with RFaVMfurther improves performance by 25%-42% for those critical services whileonly introducing up to 7% performance degradation to others, with 2%-8%more improvements in resource utilization than RAINBOW without RFaVM.

关键词： resource scheduling utility computing virtualization

来源：评论

学校读者我要写书评

暂无评论

Extracting all minimal siphons from maximal unmarked siphons in manufacturing-oriented Petri nets

Extracting all minimal siphons from maximal unmarked siphons...

引用

2011 7th IEEE International Conference on Automation Science and Engineering, CASE 2011

作者： Wang, ShouGuang Zhou, MengChu Wang, ChengYing College of Information and Electronic Engineering Zhejiang Gongshang University Hangzhou 310018 China Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102-1982 United States MoE Key Laboratory of Embedded System and Service Computing Tongji University Shanghai 200092 China

ISBN: (纸本)9781457717307

Deadlock control is an important research issue in automated manufacturing systems that have a high degree of resource sharing and concurrency. Since minimal siphons are closely tied with deadlocks in Petri net models, their efficient extraction is fundamentally important. The existing methods can rapidly extract one minimal siphon given a maximal unmarked siphon that is obtained by using a mixed integer programming approach. This paper for the first time presents an extraction algorithm that can efficiently extract all minimal ones. The idea is based on the generation and use of a subnet tree structure given the places in a maximal unmarked siphon. Several Petri net models of automated manufacturing systems are used to illustrate the proposed concepts and methods. © 2011 IEEE.

关键词： Petri nets

来源：评论

学校读者我要写书评

暂无评论

First mapping of China surface movement using supercomputing interferometric SAR technique

引用

Science Bulletin 2021年第16期66卷 1608-1610页

作者： Chao Wang Yixian Tang Hong Zhang Haihang You Weikang Zhang Wei Duan Jing Wang Longkai Dong Bo Zhang Key Laboratory of Digital Earth Science Aerospace Information Research InstituteChinese Academy of SciencesBeijing 100094China College of Resources and Environment University of Chinese Academy of SciencesBeijing 100049China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China

The Earth surface is constantly moving and changing under the influence of internal and external dynamic geological processes and human *** a time scale,such changes may occur within a few seconds,such as earthquakes and landslides,or last for several years or even longer,such as fault creep and frozen soil *** a spatial scale,such changes may manifest as local surface collapses or regional surface subsidence.

关键词： subsidence fault Earth

来源：评论

学校读者我要写书评

暂无评论

Towards memory-efficient processing-in-memory architecture for convolutional neural networks

引用

ACM SIGPLAN Notices 2017年第5期52卷 81-90页

作者： Wang, Yi Zhang, Mingxu Yang, Jing College of Computer Science and Software Engineering Shenzhen University China Experimental and Innovation Practice Center Harbin Institute of Technology Shenzhen China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

Convolutional neural networks (CNNs) are widely adopted in artificial intelligent systems. In contrast to conventional computing centric applications, the computational and memory resources of CNN applications are mixed together in the network weights. This incurs a significant amount of data movement, especially for highdimensional convolutions. Although recent embedded 3D-stacked Processing-in-Memory (PIM) architecture alleviates this memory bottleneck to provide fast near-data processing, memory is still a limiting factor of the entire system. An unsolved key challenge is how to efficiently allocate convolutions to 3D-stacked PIM to combine the advantages of both neural and computational processing. This paper presents Memolution, a compiler-based memory efficient data allocation strategy for convolutional neural networks on PIM architecture. Memolution offers thread-level parallelism that can fully exploit the computational power of PIM architecture. The objective is to capture the characteristics of neural network applications and present a hardware-independent design to transparently allocate CNN applications onto the underlining hardware resources provided by PIM. We demonstrate the viability of the proposed technique using a variety of realistic convolutional neural network applications. Our extensive evaluations show that, Memolution significantly improves performance and the cache utilization compared to the baseline scheme. © 2017 ACM.

关键词： Memory architecture

来源：评论

学校读者我要写书评

暂无评论

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture

AgileRegulator: A hybrid voltage regulator scheme redeeming ...

引用

IEEE Symposium on High-Performance computer architecture

作者： Guihai Yan Yingmin Li Yinhe Han Xiaowei Li Minyi Guo Xiaoyao Liang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Department of Computer Science and Engineering Shanghai Jiaotong University China

The widening gap between the fast-increasing transistor budget but slow-growing power delivery and system cooling capability calls for novel architectural solutions to boost energy efficiency. Leveraging the fact of surging “dark silicon” area, we propose a hybrid scheme to use both on-chip and off-chip voltage regulators, called “AgileRegulator”, for a multicore system to explore both coarse-grain and fine-grain power phases. We present two complementary algorithms: Sensitivity-Aware Application Scheduling (SAAS) and Responsiveness-Aware Application Scheduling (RAAS) to maximally achieve the energy saving potential of the hybrid regulator scheme. Experimental results show that the hybrid scheme achieves performance-energy efficiency close to per-core DVFS, without imposing much design cost. Meanwhile, the silicon overhead of this scheme is well contained into the “dark silicon”. Unlike other application specific schemes based on accelerators, the proposed scheme itself is a simple and universal solution for chip area and energy trade-offs.

关键词： system-on-a-chip Regulators Silicon Bandwidth Memory management Tuning Multicore processing

来源：评论

学校读者我要写书评

暂无评论

Integrating DBMSs as a Read-Only Execution Layer into Hadoop

Integrating DBMSs as a Read-Only Execution Layer into Hadoop

引用

IEEE International Conference on Parallel and Distributed computing, Applications and Technologies (PDCAT)

作者： Mingyuan An Yang Wang Weiping Wang Ninghui Sun Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy and Sciences Beijing China University of the Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

To obtain the efficiency of DBMS, HadoopDB combines Hadoop and DBMS, and claims the superiority over Hadoop in terms of performance. However, the approach of HadoopDB is simply putting Map Reduce onto unmodified single-machined DBMSs which has several obvious weaknesses. In essence, HadoopDB is a parallel DBMS with fault tolerance, which incurs unnecessary overhead due to the DBMS legacy. Instead of augmenting DBMS with Hadoop techniques, we propose a new system architecture integrating modified DBMS engines as a read-only execution layer into Hadoop, where DBMS plays a role of providing efficient read-only operators rather than managing the data. Besides the obtained efficiency from DBMS engine, there are other advantages. The modified DBMS engine is able to directly process data from the HDFS (Hadoop Distributed File system) files at the block level, which means that the data replication can be handled by HDFS naturally, and the block-level parallelism is easily achieved. The global index access mechanism is added according to the Map Reduce paradigm. The data loading speed is also guaranteed by directly writing the data into HDFS with simplified logic. Experiments show that our system outperforms both original Hadoop and HadoopDB styled system.

关键词： Engines Fault tolerance Fault tolerant systems Indexes Loading Parallel processing

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：