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1st International Symposium on Benchmarking, Measuring, and Optimization, Bench 2018

作者： Hao, Tianshu Huang, Yunyou Wen, Xu Gao, Wanling Zhang, Fan Zheng, Chen Wang, Lei Ye, Hainan Hwang, Kai Ren, Zujie Zhan, Jianfeng State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Dover DE United States Beijing Academy of Frontier Sciences and Technology Beijing China Chinese University of Hongkong at Shenzhen Shenzhen China Zhejiang Lab Zhejiang China

ISBN: (纸本)9783030328122

In edge computing scenarios, the distribution of data and collaboration of workloads on different layers are serious concerns for performance, privacy, and security issues. So for edge computing benchmarking, we must take an end-to-end view, considering all three layers: client-side devices, edge computing layer, and cloud servers. Unfortunately, the previous work ignores this most important point. This paper presents the BenchCouncil’s coordinated effort on edge AI benchmarks, named Edge AIBench. In total, Edge AIBench models four typical application scenarios: ICU Patient Monitor, Surveillance Camera, Smart Home, and Autonomous Vehicle with the focus on data distribution and workload collaboration on three layers. Edge AIBench is publicly available from http://***/EdgeAIBench/***. We also build an edge computing testbed with a federated learning framework to resolve performance, privacy, and security issues. © 2019, Springer Nature Switzerland AG.

关键词： Edge computing

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Optimizing MPI Alltoall Communication of Large Messages in Multicore Clusters

Optimizing MPI Alltoall Communication of Large Messages in M...

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IEEE International Conference on Parallel and Distributed computing, Applications and Technologies (PDCAT)

作者： Qiang Li Zhigang Huo Ninghui Sun Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing CN

MPI All to all communication is widely used in many high performance computing (HPC) applications. In All to all communication, each process sends a distinct message to all other participating processes. In multicore clusters, processes within a node simultaneously contend for the same network resource of the node in All to all communication. However, many small synchronization messages are required in All to all communication of large messages. With the contention, their latency is orders of magnitude larger than that without contention. As a result, the synchronization overhead is significantly increased and accounts for a large proportion to the whole latency of All to all communication. In this paper, we analyse the considerable overhead of synchronization messages. Base on the analysis, an optimization is presented to reduce the number of synchronization messages from 3N to 2¡ÌN. Evaluations on a 240-core cluster show that the performance is improved by almost constant ratio, which is mainly determined by message size and independent of system scale. The performance of All to all communication is improved by 25% for 32K and 64K bytes messages. For FFT application, performance is improved by 20%.

关键词： Synchronization Protocols Multicore processing Receivers Bandwidth Program processors Benchmark testing

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Generative artificial intelligence and its applications in materials science:Current situation and future perspectives

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Journal of Materiomics 2023年第4期9卷 798-816页

作者： Yue Liu Zhengwei Yang Zhenyao Yu Zitu Liu Dahui Liu Hailong Lin Mingqing Li Shuchang Ma Maxim Avdeev Siqi Shi School of Computer Engineering and Science Shanghai UniversityShanghai200444China State Key Laboratory of Advanced Special Steel School of Materials Science and EngineeringShanghai UniversityShanghai200444China Materials Genome Institute Shanghai UniversityShanghai200444China Shanghai Engineering Research Center of Intelligent Computing System Shanghai200444China Australian Nuclear Science and Technology Organisation Sydney2232Australia School of Chemistry The University of SydneySydney2006Australia

Generative Artificial Intelligence(GAI)is attracting the increasing attention of materials community for its excellent capability of generating required *** the introduction of Prompt paradigm and reinforcement learning from human feedback(RLHF),GAI shifts from the task-specific to general pattern gradually,enabling to tackle multiple complicated tasks involved in resolving the structure-activity ***,we review the development status of GAI comprehensively and analyze pros and cons of various generative models in the view of *** applications of task-specific generative models involving materials inverse design and data augmentation are also *** ChatGPT as an example,we explore the potential applications of general GAI in generating multiple materials content,solving differential equation as well as querying materials ***,we summarize six challenges encountered for the use of GAI in materials science and provide the corresponding *** work paves the way for providing effective and explainable materials data generation and analysis approaches to accelerate the materials research and development.

关键词： Machine learning Artificial intelligence Generative artificial intelligence Materials science Novel materials discovery Deep learning

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Online timing variation tolerance for digital integrated circuits

Online timing variation tolerance for digital integrated cir...

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IEEE International Test Conference

作者： Guihai Yan Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Beijing China

Ensuring safe timing increasingly becomes a paramount challenge with the technology scaling to nanoscale. This study aims to provide timing variation detection and tolerance solutions. We first propose a versatile online timing variation detection scheme which can handle multiple types of faults. With the capability of detection, we further propose two tolerance schemes to eliminate runtime margin in DVFS applications and improve lifetime reliability under progressive aging mechanisms, respectively. Lastly, given the more complicated PVT variations whose primary circuit implication is also timing variations, we propose TEA-TM, a novel architectural scheme to reduce timing emergencies. Collectively, we aims to build a comprehensive framework for timing variation tolerance and demonstrate several specific applications.

关键词： Delay Aging Circuit faults Circuit stability Sensors Stability analysis

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M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induce...

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Asian Test Symposium (ATS)

作者： Song Jin Yinhe Han Lei Zhang Huawei Li Xiaowei Li Guihai Yan Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architeture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time and in turn degrading the circuit performance. NBTI degradation has strong dependence on input pattern and duty cycles. Based on this observation, we propose to apply multiple input vectors to the combination circuit in a non-uniform way during standby mode. Multiple input vectors can enhance the capability to control the circuit nodes, achieve smaller duty cycles to reduce the stress time of gates and thus mitigate static NBTI. A constrained multi-object optimization model is formalized to find the optimal combination of duty cycles for timing-critical paths, which in turn minimizes the increase of path delay. An ATPG-like procedure is then presented to generate the corresponding input vectors. Experimental results demonstrate that the delay increase of timing-critical paths can be mitigated significantly under long time NBTI effect (10-year) by only applying a small number of vectors.

关键词： Niobium compounds Titanium compounds Degradation Stress Delay effects Circuits Threshold voltage Clocks Resists Aging

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A Fault Criticality Evaluation Framework of Digital systems for Error Tolerant Video Applications

A Fault Criticality Evaluation Framework of Digital Systems ...

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Asian Test Symposium (ATS)

作者： Yuntan Fang Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Error tolerance is evolving into a new computing paradigm with further technology scaling, cost constraint, system scalability and emerging applications. Distinguished from defect tolerance and fault tolerance, error tolerance is based on application characteristics and relaxes the constraint of 100 percent functional correctness. From the viewpoint of error tolerance, this paper proposes a framework across multiple layers for fault criticality evaluation. Furthermore, taking an H.264/AVC decoder as an example, fault injection experiments demonstrate that for different functional modules, the faults in them bear different fault criticalities because of their unbalanced effects on applications, the faults in the same module also have diverse fault criticalities. The information that which faults are most critical can aid in test for yield and design for cost-effective fault tolerance. Error control techniques can be used to suppress error propagation and make more faults acceptable.

关键词： Circuit faults Decoding Video sequences Measurement PSNR Fault diagnosis Transform coding

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A lightweight hybrid hardware/software approach for object-relative memory profiling

A lightweight hybrid hardware/software approach for object-r...

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IEEE International Symposium on Performance Analysis of systems and Software

作者： Licheng Chen Zehan Cui Yungang Bao Mingyu Chen Yongbing Huang Guangming Tan Graduate School of Chinese Academy of Sciences China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781467311434

Memory profiling is the process of collecting memory address traces during the execution of a program, then analyzing and characterizing the memory behavior of the program offline. With the trend that there will be more and more cores integrated in a processor chip, the “Memory Wall” problem will become more serious in the chip multiprocessor (CMP) system. Thus accurate and effective memory profiling is becoming one of the keys to identify the source of memory system bottlenecks. A large body of work has been contributed to memory profiling, however, most adopts instrumentation, simulator which suffers heavy overhead, or hardware performance counter which is lack of detail trace information. Furthermore, correlating the raw memory address traces with object-relative information allows us to separate regular pattern for certain object from the irregular mixed, thus helps the optimization. In this paper, we propose a lightweight hybrid hardware/software approach for object-relative memory profiling. We monitor physical memory addresses through hardware snooping with negligible overhead; meanwhile we dump Linux kernel page tables of processes, as well as object-relative memory allocation information. Our approach supports not only to collect applications' full memory traces with detail object relative information, but also to identify hardware-generated memory accesses such as page memory walks due to TLB miss at object level. The experimental results on real system show that our approach is highly accurate (the largest error is 2.04%) and low overhead (the average overhead is 1.60%). Furthermore, we profile two multi-thread applications in detail, and successfully identity hot TLB-miss objects. With object-targeted optimization, we can improve applications' performance by nearly 6.86%.

关键词： Kernel Hardware Monitoring Optimization Linux Arrays

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SEIMI: Efficient and Secure SMAP-Enabled Intra-process Memory Isolation

SEIMI: Efficient and Secure SMAP-Enabled Intra-process Memor...

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IEEE Symposium on Security and Privacy

作者： Zhe Wang Chenggang Wu Mengyao Xie Yinqian Zhang Kangjie Lu Xiaofeng Zhang Yuanming Lai Yan Kang Min Yang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences The Ohio State University University of Minnesota Fudan University

ISBN: (数字)9781728134970

ISBN: (纸本)9781728134987

Memory-corruption attacks such as code-reuse attacks and data-only attacks have been a key threat to systems security. To counter these threats, researchers have proposed a variety of defenses, including control-flow integrity (CFI), code-pointer integrity (CPI), and code (re-)randomization. All of them, to be effective, require a security primitive-intra-process protection of confidentiality and/or integrity for sensitive data (such as CFI's shadow stack and CPI's safe region).In this paper, we propose SEIMI, a highly efficient intra-process memory isolation technique for memory-corruption defenses to protect their sensitive data. The core of SEIMI is to use the efficient Supervisor-mode Access Prevention (SMAP), a hardware feature that is originally used for preventing the kernel from accessing the user space, to achieve intra-process memory isolation. To leverage SMAP, SEIMI creatively executes the user code in the privileged mode. In addition to enabling the new design of the SMAP-based memory isolation, we further develop multiple new techniques to ensure secure escalation of user code, e.g., using the descriptor caches to capture the potential segment operations and configuring the Virtual Machine Control Structure (VMCS) to invalidate the execution result of the control registers related operations. Extensive experimental results show that SEIMI outperforms existing isolation mechanisms, including both the Memory Protection keys (MPK) based scheme and the Memory Protection Extensions (MPX) based scheme, while providing secure memory isolation.

关键词： Hardware Kernel Security Runtime Registers Data structures Switches

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VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack

VADER: Leveraging the Natural Variation of Hardware to Enhan...

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Asia and South Pacific Design Automation Conference

作者： Hao Lv Bing Li Ying Wang Cheng Liu Lei Zhang Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Capital Normal University State Key Laboratory of Computer Architecture

ISBN: (数字)9781450379991

ISBN: (纸本)9781728180571

Adversarial attacks have been viewed as the primary threat to the security of neural networks. Hence, extensive adversarial defense techniques have been proposed to protect the neural networks from adversarial attacks, allowing for the application of neural networks to the security-sensitive tasks. Recently, the emerging devices, e.g., Resistive RAM (RRAM), attracted extensive attention for establishing the hardware platform for neural networks to tackle the inadequate computing capability of the traditional computing platform. Though the emerging devices exhibit the instinct instability issues due to the advanced manufacture technology, including hardware variations and defects, the error-resilience capability of neural networks enables the wide deployment of neural networks on the emerging devices. In this work, we find that the natural instability in emerging devices impairs the security of neural networks. Specifically, we design an enhanced adversarial attack, Variation-oriented ADvERsarial (VADER) attack which leverages the inherent hardware variations in RRAM chips to penetrate the protection of adversarial defenses and mislead the prediction of neural networks. We evaluated the effectiveness of VADER across various protected neural network models and the result shows that VADER achieves higher success attack rate over other adversarial attacks.

关键词： Semiconductor lasers Neural networks Resistive RAM Hardware Security Laser beams Task analysis

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An Auto-Parallel Method for Deep Learning Models Based on Genetic Algorithm 29

An Auto-Parallel Method for Deep Learning Models Based on Ge...

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29th IEEE International Conference on Parallel and Distributed systems, ICPADS 2023

作者： Zeng, Yan Huang, Chengchuang Ni, Yijie Zhou, Chunbao Zhang, Jilin Wang, Jue Zhou, Mingyao Xue, Meiting Zhang, Yunquan Hangzhou Dianzi University School of Computer Science and Technology Hangzhou310018 China Ministry of Education Key Laboratory for Modeling and Simulation of Complex Systems Hangzhou310018 China Data Security Governance Zhejiang Engineering Research Center Hangzhou310018 China Hangzhou Dianzi University School of ITMO Joint Institute Hangzhou310018 China Institute of Computer Network Information Center of the Chinese Academy of Sciences Beijing100086 China HuaWei China Institute of Computing Technology of the Chinese Academy of Sciences State Key Laboratory of Computer Architecture Beijing100086 China

ISBN: (纸本)9798350330717

As the size of datasets and neural network models increases, automatic parallelization methods for models have become a research hotspot in recent years. The existing auto-parallel methods based on machine learning or graph algorithms still have issues with search efficiency and applicability. This paper proposes an automatic parallel method based on a dual-population genetic algorithm, TGA, which transforms model partitioning and placement into an integer linear programming problem and constructs a cost model to evaluate the solution. The solution space is built using the neural network's dataflow graph and device cluster's topology, and the dual-population genetic algorithm is used to search for the optimal model parallel strategy. Experiments with various models show that the proposed method can improve single-step execution time by up to 42% compared to the Baechi method and up to 37.7% compared to the Hierarchical method. © 2023 IEEE.

关键词： Auto-Parallel Distributed machine learning Genetic algorithm Integer linear programming Model parallelism

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