检索结果-内蒙古大学图书馆

IEEE VLSI Test Symposium (VTS)

作者： Tao Lv Hua-wei Li Xiao-wei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781424437696

As the design complexity increases dramatically, results of functional simulation are usually checked through only a part of signals during design verification. It is important, therefore, to consider the observability of internal signals for effective checking. This paper proposes a static observability analysis method to automatically select internal observation signals, which improves the quality of functional verification. A series of formulas are defined to evaluate observability of internal signals, and an algorithm is proposed to locate the sources of low-observability. Such sources, rather than general hard-to-observe signals, are desirable internal observation signals. Experimental results indicate that signals selected by this method can improve the observability of designs more than those randomly selected from hard-to-observe signals.

关键词： Internal observation signals Design verification Static analysis

来源：评论

学校读者我要写书评

暂无评论

P2CLRAF: An Pre-and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework

P2CLRAF: An Pre-and Post-silicon Cooperated Circuit Lifetime...

引用

2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Song Jin Yinhe Han Huawei Li Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing P.R. China Graduate University of Chinese Academy of Sciences Beijing P.R. China

Statistical static timing analysis (SSTA) considering process variation and aging effects is usually used to analyze circuit lifetime reliability at design phase. A key challenge for statistical lifetime reliability analysis is that an accurate statistical timing model is needed to carefully model practical variation distribution as well as delay correlation. In this work, P2CLRAF, a circuit lifetime reliability analysis framework is proposed. It calibrates presilicon SSTA result by learning the collected data from path delay testing at post-silicon timing validation phase. A neural network inside P2CLRAF is trained to learn variation distribution and delay correlation based on the statistic of path delay testing. The learned information is then fed back to SSTA to further improve the accuracy of circuit lifetime reliability analysis. Experimental results demonstrate the effectiveness of the proposed analysis framework.

关键词： Lifetime Reliability Process Variation NBTI

来源：评论

学校读者我要写书评

暂无评论

An 8-bit Bit-Slice TEA-Cryptographic Accelerator for 64-bit RSFQ Secure Coprocessors

An 8-bit Bit-Slice TEA-Cryptographic Accelerator for 64-bit ...

引用

IEEE International Superconductive Electronics Conference (ISEC)

作者： Pei-Shi Yu Guang-Ming Tang Xiao-Chun Ye Dong-Rui Fan Zhi-Min Zhang Ning-Hui Sun University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

An 8-bit bit-slice TEA-cryptographic accelerator for 64-bit RSFQ secure coprocessors is proposed. The accelerator is based on Tiny Encryption Algorithm (TEA) and mainly consists of bit-slice adders and bit-slice shifters. Synchronous concurrent-flow clocking is used to design a fully pipelined RSFQ logic design. For verifying the algorithm and the logic design, the RSFQ logic circuits of the proposed accelerator have been simulated with a target operating frequency of 50 GHz. It consists of 21 stages. The throughput is 7.672 × 10 7 64-bit TEA encryptions per second.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Dynamic register promotion of stack variables 11

Dynamic register promotion of stack variables

引用

International Symposium on Code Generation and Optimization (CGO)

作者： Jianjun Li Chenggang Wu Wei-Chung Hsu Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Deparunent of Computer Science National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781612843568

Dynamic Binary Translation (DBT) has been widely used in various applications. Although new architectures and micro-architectures often create performance opportunities for programmers and compilers, such performance opportunities may not be exploited by legacy executables. For example, the additional general-purpose and XMM registers in the Intel64 architecture do not benefit the IA-32 binaries. In this paper, we designed and developed a DBT system to dynamically promote stack variables in the source binaries to the additional registers of the target architecture. One of the most challenging problems is how to deal with the possible but rare memory aliases between promoted stack variables and other implicit memory references. We devised a runtime alias detection approach based on the page protection mechanism in Linux and a novel stack switching method to catch memory aliases at run-time. This approach is much less expensive than traditional approaches like inserting address checking instructions. On an Intel64 platform, our DBT system with speculative stack variable promotion has sped up several SPEC CPU2006 benchmarks in IA-32 code, with the largest performance gain over 45%.

关键词： Registers Optimization Switches computer architecture Benchmark testing Runtime Program processors

来源：评论

学校读者我要写书评

暂无评论

Logic Design of an 8-bit RSFQ Microprocessor

Logic Design of an 8-bit RSFQ Microprocessor

引用

IEEE International Superconductive Electronics Conference (ISEC)

作者： Jia-Hong Yang Guang-Ming Tang Pei-Yao Qu Xiao-Chun Ye Dong-Rui Fan Zhi-Min Zhang Ning-Hui Sun University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

An 8-bit bit-parallel RSFQ microprocessor, named HUTU, is proposed. It can execute 28 different instructions. Each instruction consists of eight bits. Harvard-type architecture is adopted for parallel processing between the control unit and the datapath. The control unit uses an asynchronous timing method to avoid pipeline flushing and to reduce the area. Concurrent-flow clocking is adopted in the datapath for high performance. The simulation result shows that the elements of HUTU run correctly.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Efficient dynamic evolution of service composition

Efficient dynamic evolution of service composition

引用

作者： Lv, Chen Jiang, Wei Hu, Songlin Wang, Jiye Lu, Guoliang Liu, Zhiyong School of Information Science and Engineering Shandong Normal University China Greatwall Drilling Company R&D Academy of Well Logging CNPC Beijing China Institute of Information Engineering Chinese Academy of Sciences Beijing China Department of Information Technology State Grid Corporation of China Beijing China School of Mechanical Engineering Shandong University China Institute of Computing Technology Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

Current QoS-aware automatic service composition queries over a network of web services are often one-time in nature. After a network of web services is built, such queries are issued once, and answers are found from the scratch. The underlying assumption is that the participating web services are rather static, which means that their functional and non-functional parameters seldom change. However, such an assumption is often baseless. New services come and go, service APIs change gradually, and QoS values fluctuate in practice. Therefore, a support for efficiently adapting service composition is desired. In this paper, we propose an event driven continuous query algorithm to intelligently cope with different types of dynamic services, and thus enable evolution of service composition. Evaluation using both real QoS data and synthetic web service data shows its superior performance, compared with the state-of-the-art solution which won the performance championship of Web Service Challenge in 2009 and 2010. Moreover, we generalize a new graph problem: dynamic single-source optimal-Directed Acyclic Graphs (DAG) problem based on the above work. It is argued that API recommendation for framework evolution, as another typical application, could also be modeled and addressed efficiently using the proposed new graph approach. © 2017 IEEE.

关键词： Web services

来源：评论

学校读者我要写书评

暂无评论

Automatic Implementation of Multi-partitioning Using Global Tiling

Automatic Implementation of Multi-partitioning Using Global ...

引用

International Conference on Parallel and Distributed systems (ICPADS)

作者： Lei Liu Dingfei Zhang Hengjie Li Li Chen Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Strategies for partitioning an application¿s data and computation play fundamental role in determining the efficiency of parallelization. This paper describes a sophisticated strategy for partitioning data and computation known as multi-partitioning, which can support the best parallelization for some applications such as the line sweep computations. However, the implementation of multi-partitioning is very difficult and, as we know, there is none automatic parallelizing compiler supports such partitioning strategy. Though the dHPF compiler implemented multi-partitioning as a special extension for block style HPF partitioning, it still needs the programmer¿s participation to analyze the application and decide the data distribution scheme. In this paper, we present a global tiling transformation algorithm and a tile-to-processors mapping strategy called hyper-diagonal modular mapping, to implement the multi-partitioning strategy. The experimentation with NPB2.3-serial SP shows that the code generated by the compiler achieves scalable performance.

关键词： Concurrent computing Distributed computing computer applications Program processors Partitioning algorithms Tiles Laboratories computer architecture Partial differential equations Navier-Stokes equations

来源：评论

学校读者我要写书评

暂无评论

Logic Design of a 16-bit Bit-Slice Shifter for 64-bit RSFQ Microprocessors

Logic Design of a 16-bit Bit-Slice Shifter for 64-bit RSFQ M...

引用

IEEE International Superconductive Electronics Conference (ISEC)

作者： Wei Xuan Guang-Ming Tang Pei-Yao Qu Zhi-Min Tang Xiao-Chun Ye Dong-Rui Fan Zhi-Min Zhang Ning-Hui Sun University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Logic design of a 16-bit bit-slice shifter for 64-bit superconducting rapid single-flux-quantum (RSFQ) microprocessors is proposed. The shifter supports three types of shift operations including logic shift, arithmetic shift and rotating shift. Each of 64-bit shift input operands is divided into four slices of 16-bit each. In order to simulate the digital function and timing of the proposed 16-bit bit-slice shifter, we design a logic-level simulation model based on the Open Dataset of CONNECT Cell Library for AIST ADP2. As the results of simulation, the information of RSFQ circuits, such as the number of Josephson junctions, area and latency of the 16-bit bit slice shifter can be obtained. The simulation results show that the proposed 16-bit bit-slice shifter can work correctly.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Auto-tuning neural network quantization framework for collaborative inference between the cloud and edge

arXiv

引用

arXiv 2018年

作者： Li, Guangli Liu, Lei Wang, Xueying Dong, Xiao Zhao, Peng Feng, Xiaobing State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

Recently, deep neural networks (DNNs) have been widely applied in mobile intelligent applications. The inference for the DNNs is usually performed in the cloud. However, it leads to a large overhead of transmitting data via wireless network. In this paper, we demonstrate the advantages of the cloud-edge collaborative inference with quantization. By analyzing the characteristics of layers in DNNs, an auto-tuning neural network quantization framework for collaborative inference is proposed. We study the effectiveness of mixed-precision collaborative inference of state-of-the-art DNNs by using ImageNet dataset. The experimental results show that our framework can generate reasonable network partitions and reduce the storage on mobile devices with trivial loss of accuracy. Copyright © 2018, The Authors. All rights reserved.

关键词： Deep neural networks

来源：评论

学校读者我要写书评

暂无评论

Design of Datapath Circuits for a Bit-Parallel 8-bit RSFQ Microprocessor

Design of Datapath Circuits for a Bit-Parallel 8-bit RSFQ Mi...

引用

IEEE International Superconductive Electronics Conference (ISEC)

作者： Pei-Yao Qu Guang-Ming Tang Xiao-Chun Ye Dong-Rui Fan Zhi-Min Zhang Ning-Hui Sun University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Rapid single-flux-quantum (RSFQ) is expected to be the next generation integrated circuit technology because of its ultra-high-speed with ultra-low-power consumption. We propose datapath circuits for an 8-bit bit-parallel RSFQ microprocessor. The proposed datapath circuits process 8-bit data each clock cycle. Seven instructions are executed in the datapath, including ADD, ADDI, IN, OUT, LOADI, SRL and MOV. The datapath circuits consist of eight input ports, eight output ports, five multiplexers (MUXs), two 8-bit data registers and one 8-bit bit-parallel arithmetic logic unit (ALU). The datapath circuits contain 12 pipeline stages and 2993 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2 without considering wiring cells. We perform digital simulation of the proposed datapath circuits. The simulation results show correct operation with the assumed frequency of 20 GHz.

关键词：

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：