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SCIENTISTS RECONSIDER LOW-ENERGY NUCLEAR REACTIONS It's absolutely, definitely, seriously not cold fusion

IEEE SPECTRUM 2018年第12期55卷 10-11页

作者： Koziol, Michael State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences

It's been a big year for low-energy nuclear reactions. LENRs, as they're known, are a fringe research topic that some physicists think could explain the results of an infamous experiment nearly 30 years ago that formed the basis for the idea of cold fusion. That idea didn't hold up, and only a handful of researchers around the world have continued trying to understand the mysterious nature of the inconsistent, heat-generating reactions that had spurred those claims.

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A parallel algorithm for computing betweenness centrality

A parallel algorithm for computing betweenness centrality

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38th International Conference on Parallel Processing, ICPP-2009

作者： Tan, Guangming Tu, Dengbiao Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769538020

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n + m) space and O(nm/p ) ( or O(nm+n2logn /p )) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times. © 2009 IEEE.

关键词： Parallel algorithms

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Software and hardware cooperate for 1-D FFT algorithm optimization on multicore processors

Software and hardware cooperate for 1-D FFT algorithm optimi...

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IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Zhou, Yongbin Zhang, Junchao Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier Transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency. © 2009 IEEE.

关键词： Fast Fourier transforms

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Circuit implementation of floating point range reduction for trigonometric functions

Circuit implementation of floating point range reduction for...

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2007 IEEE International Symposium on Circuits and systems, ISCAS 2007

作者： Xuehai, Qian Hao, Zhang Jingang, Yang He, Huang Junchao, Zhang Dongrui, Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Range reduction is important in evaluating trigonometric functions but not enough work is done in relation to the hardware implementation of it. A hardware floating point range reduction implementation is presented. The whole reduction is divided into two steps;the first is based on Double-Residue modular range reduction method and the second adopts on a novel method described in this paper. The latter one can reduce the argument to an arbitrary range and provides the number of times that range constant contained in the argument It has been synthesized using 0.13 um library to achieve an approximately 700 MHz operation frequency. © 2007 IEEE.

关键词： Digital circuits

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Snooping and ordering ring - An efficient cache coherence protocol for ring connected CMP

Snooping and ordering ring - An efficient cache coherence pr...

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15th International Conference on Parallel and Distributed systems, ICPADS '09

作者： Cao, Fei Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769539003

Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. Existing ring protocols, such as the snooping ring protocol and the ring-order protocol need a retry and acknowledgement scheme or use the ordering property of the ring respectively to resolve conflict memory requests. A cache coherence protocol named SOR (Snooping and Ordering Ring) is developed for ring connected CMP in this paper. This protocol is based on the snooping ring protocol. But instead of using the acknowledgement and retry scheme, it uses the ordering property of the ring to resolve conflicts, thus can avoid unnecessary retries to improve performance and power efficiency. The L1 snooping results are sent with the requests instead of being delayed, so that many useless snoops can be avoided. Simulation result shows that the average probe slot transports and snoop operations can be reduced by SOR are 47% and 48.9%. The average and maximum performance improvements by SOR are 3.33% and 6%. © 2009 IEEE.

关键词： Packet switching

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Dynamic data-sharing based user recruitment in mobile crowdsensing

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High technology Letters 2019年第1期25卷 8-16页

作者： Chen Shuang Liu Min Sun Sheng Jiao Zhenzhen State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

Mobile crowdsensing(MCS) has become an emerging paradigm to solve urban sensing problems by leveraging the ubiquitous sensing capabilities of the crowd. One critical issue in MCS is how to recruit users to fulfill more sensing tasks with budget restriction, while sharing data among tasks can be a credible way to improve the efficiency. The data-sharing based user recruitment problem under budget constraint in a realistic scenario is studied, where multiple tasks require homogeneous data but have various spatio-temporal execution ranges, meanwhile users suffer from uncertain future positions. The problem is formulated in a manner of probability by predicting user mobility, then a dynamic user recruitment algorithm is proposed to solve it. In the algorithm a greedy-adding-and-substitution(GAS) heuristic is repeatedly implemented by updating user mobility prediction in each time slot to gradually achieve the final solution. Extensive simulations are conducted using a real-world taxi trace dataset, and the results demonstrate that the approach can fulfill more tasks than existing methods.

关键词： mobile crowdsensing(MCS) data sharing user recruitment mobility prediction dynamic decision

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Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

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Journal of computer Science & technology 2007年第1期22卷 1-14页

作者：胡伟武赵继业钟石强杨旭 Elio Guidetti 吴永强 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

关键词： general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design,synthesis flow bit-sliced placement crafted cell performance evaluation

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Fuzzy Granule Density-Based Outlier Detection with Multi-Scale Granular Balls

arXiv

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arXiv 2025年

作者： Gao, Can Tan, Xiaofeng Zhou, Jie Ding, Weiping Pedrycz, Witold The College of Computer Science and Software Engineering Shenzhen University Shenzhen518060 China Guangdong Key Laboratory of Intelligent Information Processing Shenzhen518060 China The National Engineering Laboratory for Big Data System Computing Technology Shenzhen University Shenzhen518060 China The School of Artificial Intelligence and Computer Science Nantong University Nantong226019 China The Faculty of Data Science City University of Macau Macau999078 China The Department of Electrical and Computer Engineering University of Alberta Edmonton Canada Systems Research Institute Polish Academy of Sciences Warsaw Poland The Department of Electrical and Computer Engineering King Abdulaziz University Jeddah Saudi Arabia The Department of Computer Engineering Istinye University Istanbul Turkey

Outlier detection refers to the identification of anomalous samples that deviate significantly from the distribution of normal data and has been extensively studied and used in a variety of practical tasks. However, most unsupervised outlier detection methods are carefully designed to detect specified outliers, while real-world data may be entangled with different types of outliers. In this study, we propose a fuzzy rough sets-based multi-scale outlier detection method to identify various types of outliers. Specifically, a novel fuzzy rough sets-based method that integrates relative fuzzy granule density is first introduced to improve the capability of detecting local outliers. Then, a multi-scale view generation method based on granular-ball computing is proposed to collaboratively identify group outliers at different levels of granularity. Moreover, reliable outliers and inliers determined by the three-way decision are used to train a weighted support vector machine to further improve the performance of outlier detection. The proposed method innovatively transforms unsupervised outlier detection into a semi-supervised classification problem and for the first time explores the fuzzy rough sets-based outlier detection from the perspective of multi-scale granular balls, allowing for high adaptability to different types of outliers. Extensive experiments carried out on both artificial and UCI datasets demonstrate that the proposed outlier detection method significantly outperforms the state-of-the-art methods, improving the results by at least 8.48% in terms of the Area Under the ROC Curve (AUROC) index. The source codes are released at https://***/Xiaofeng-Tan/MGBOD. © 2025, CC BY.

关键词： Granulation

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DimRouter： A Multi-Mode Router architecture for Higher Energy-Proportionality of On-Chip Networks

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Journal of computer Science & technology 2018年第5期33卷 984-997页

作者： Shi-Qi Lian Ying Wang Yin-He Han State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

In the dark silicon era, many independent components of many-core processors are becoming voluntarily inactive due to the constraint of power consumption on a chip. However, to keep network connectivity, the on-chip interconnection must still be kept activated and wastes considerable energy to avoid the isolation of these inactive components, harming the energy-proportionality of the whole processor chip. In this paper, we propose a novel design to provide more energy- proportional on-chip connection without damaging the network connectivity. To achieve this goal, we redesign the router architecture. The new architecture, DimRouter, supports three modes： normal, dark and dim. In the dim mode, only part of the router is active and provides flexible connection while the dark mode puts all router elements in the asleep state. Moreover, to maximize the number of dark routers, we also propose a reconfiguration algorithm based on degree-constrained Steiner Tree. The evaluation result under synthetic traffic shows that the new design can reduce the energy consumption up to 85% compared with the common design. For real application traffic, the new design can also save average 46% energy consumption with 4% performance improvement.

关键词： dark silicon energy-proportion power gating topology reconfiguration

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Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage computing

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Journal of computer Science & technology 2016年第2期31卷 253-266页

作者： Xin He Gui-Hai Yan Yin-He Han Xiao-Wei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

The load power range of modern processors is greatly enlarged because many advanced power management techniques are employed, such as dynamic voltage frequency scaling, Turbo Boosting, and near-threshold voltage （NTV） technologies. However, because the efficiency of power delivery varies greatly with different load conditions, conventional power delivery designs cannot maintain high efficiency over the entire voltage spectrum, and the gained power saving may be offset by power loss in power delivery. We propose SuperRange, a wide operational range power delivery unit. SuperRange complements the power delivery capability of on-chip voltage regulator and off-chip voltage regulator. On top of SuperRange, we analyze its power conversion characteristics and propose a voltage regulator （VR） aware power management algorithm. Moreover, as more and more cores have been integrated on a singe chip, multiple SuperRange units can serve as basic building blocks to build, in a highly scalable way, more powerful power delivery subsystem with larger power capacity. Experimental results show SuperRange unit offers lx and 1.3x higher power conversion efficiency （PCE） than other two conventional power delivery schemes at NTV region and exhibits an average 70% PCE over entire operational range. It also exhibits superior resilience to power-constrained systems.

关键词： voltage regulator power delivery near-threshold computing multicore processor

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