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检索条件"机构=Key Laboratory of Computer System and Architecture Institute of Computing Technology"
1006 条 记 录,以下是691-700 订阅
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An ultra-fast hybrid simulation framework for ASIP
An ultra-fast hybrid simulation framework for ASIP
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2011 18th IEEE International Conference on Electronics, Circuits and systems, ICECS 2011
作者: Qiu, Ji Gao, Xiang Jiang, Yifei Xiao, Xu Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Science Beijing 100190 China Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana IL United States
ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In... 详细信息
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Optimizing web browser on many-core architectures
Optimizing web browser on many-core architectures
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2011 12th International Conference on Parallel and Distributed computing, Applications and Technologies, PDCAT 2011
作者: Fan, Lingjun Shi, Weisong Tang, Shibin Yan, Chenggang Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Academy of Sciences Graduate University Beijing China Department of Computer Science Wayne State University Detroit United States
As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more perfo... 详细信息
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Cross-layer optimized placement and routing for FPGA soft error mitigation
Cross-layer optimized placement and routing for FPGA soft er...
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作者: Huang, Keheng Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China
As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placem... 详细信息
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A cost-effective substantial-impact-filter based method to tolerate voltage emergencies
A cost-effective substantial-impact-filter based method to t...
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作者: Pan, Songjun Hu, Yu Hu, Xing Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China
Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizin... 详细信息
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On diagnosis of multiple faults using compacted responses
On diagnosis of multiple faults using compacted responses
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作者: Ye, Jing Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China
With the exponential growth in the number of transistors, not only test data volume and test application time may increase, but also multiple faults may exist in one chip. Test compaction has been a de-facto design-fo... 详细信息
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A Case Study: Low Power Design-for-Testability Features of a Multi-core Processor Godson-T
A Case Study: Low Power Design-for-Testability Features of a...
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2011 2nd International Conference on Advanced Measurement and Test (AMT 2011)
作者: Da Wang Dongrui Fan Yu Hu Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences
This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical coresSince the silicon design technology scales to ultra deep submicron and even nanomet... 详细信息
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Processes scheduling on heterogeneous multi-core architecture with hardware support
Processes scheduling on heterogeneous multi-core architectur...
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IEEE International Conference on Networking, architecture and Storage
作者: Hao, Shouqing Liu, Qi Zhang, Longbing Wang, Jian Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China
Heterogeneous Chip Multi-Processors (heter-CMP) provide suitable resources to various applications and could get more benefits on performance than homogeneous CMP. To fully develop the performance of the heter-CMP sys... 详细信息
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A fine-grained component-level power measurement method
A fine-grained component-level power measurement method
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2011 International Green computing Conference, IGCC 2011
作者: Cui, Zehan Zhu, Yan Bao, Yungang Chen, Mingyu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate School of Chinese Academy of Sciences Beijing China
The ever growing energy consumption of computer systems have become a more and more serious problem in the past few years. Power profiling is a fundamental way for us to better understand where, when and how energy is... 详细信息
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An efficient shared memory based virtual communication system for embedded SMP cluster
An efficient shared memory based virtual communication syste...
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IEEE International Conference on Networking, architecture and Storage
作者: Yin, Wenxuan Gao, Xiang Zhu, Xiaojing Guo, Deyuan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Loongson Technology Corporation Limited Beijing China Institute of Microelectronics Tsinghua University Beijing China
With the prevalence of multi-core processors, it is a trend that the embedded cluster deploys SMP nodes to gain more computing power. As a crucial issue, the MPI interprocess communication has been suffering the contr... 详细信息
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Empirical design bugs prediction for verification
Empirical design bugs prediction for verification
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作者: Guo, Qi Chen, Tianshi Shen, Haihua Chen, Yunji Wu, Yue Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Beijing 100049 China Loongson Technologies Corporation Limited Beijing 100190 China
Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is ... 详细信息
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